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Class Information
Number: 711/212
Name: Electrical computers and digital processing systems: memory > Address formation > Varying address bit-length or size
Description: Subject matter wherein bits are added or subtracted from existing address data
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7610466 |
Data processing system using independent memory and register operand size specifiers and method thereof |
Oct. 27, 2009 |
| 7610447 |
Upgradable memory system with reconfigurable interconnect |
Oct. 27, 2009 |
| 7603493 |
Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction |
Oct. 13, 2009 |
| 7587571 |
Evaluation unit in an integrated circuit |
Sep. 8, 2009 |
| 7577789 |
Upgradable memory system with reconfigurable interconnect |
Aug. 18, 2009 |
| 7571076 |
Performance monitor device, data collecting method and program for the same |
Aug. 4, 2009 |
| 7546410 |
Self timed memory chip having an apportionable data bus |
Jun. 9, 2009 |
| 7533241 |
Variable size cache memory support within an integrated circuit |
May. 12, 2009 |
| 7502908 |
Method for providing an address format compatible with different addressing formats used for addressing different sized address spaces |
Mar. 10, 2009 |
| 7493456 |
Memory queue with supplemental locations for consecutive addresses |
Feb. 17, 2009 |
| 7475219 |
Serially indexing a cache memory |
Jan. 6, 2009 |
| 7464249 |
System and method for alias mapping of address space |
Dec. 9, 2008 |
| 7451292 |
Methods for transmitting data across quantum interfaces and quantum gates using same |
Nov. 11, 2008 |
| 7447871 |
Data access program instruction encoding |
Nov. 4, 2008 |
| 7404055 |
Memory transfer with early access to critical portion |
Jul. 22, 2008 |
| 7404049 |
Method and system for managing address bits during buffered program operations in a memory device |
Jul. 22, 2008 |
| 7401202 |
Memory addressing |
Jul. 15, 2008 |
| 7395412 |
Apparatus and method for extending data modes in a microprocessor |
Jul. 1, 2008 |
| 7386700 |
Virtual-to-physical address translation in a flash file system |
Jun. 10, 2008 |
| 7386650 |
Memory test circuit with data expander |
Jun. 10, 2008 |
| 7356811 |
Method and apparatus for referencing a constant pool in a java virtual machine |
Apr. 8, 2008 |
| 7340501 |
System, method, apparatus and program for collecting and providing information |
Mar. 4, 2008 |
| 7337300 |
Procedure for processing a virtual address for programming a DMA controller and associated system on a chip |
Feb. 26, 2008 |
| 7290078 |
Serial memory comprising means for protecting an extended memory array during a write operation |
Oct. 30, 2007 |
| 7277399 |
Hardware-based route cache using prefix length |
Oct. 2, 2007 |
| 7272699 |
Flexible sub-column to sub-row mapping for sub-page activation in XDR.TM. DRAMs |
Sep. 18, 2007 |
| 7269711 |
Methods and apparatus for address generation in processors |
Sep. 11, 2007 |
| 7266667 |
Memory access using multiple sets of address/data lines |
Sep. 4, 2007 |
| 7257643 |
Method and apparatus to improve network routing |
Aug. 14, 2007 |
| 7246198 |
Content addressable memory with programmable word width and programmable priority |
Jul. 17, 2007 |
| 7240180 |
Method and system for simultaneously supporting different block sizes on a single hard drive |
Jul. 3, 2007 |
| 7191309 |
Double shift instruction for micro engine used in multithreaded parallel processor architecture |
Mar. 13, 2007 |
| 7185324 |
Compiler apparatus and method for determining locations for data in memory area |
Feb. 27, 2007 |
| 7181591 |
Memory address decoding method and related apparatus by bit-pattern matching |
Feb. 20, 2007 |
| 7171543 |
Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor |
Jan. 30, 2007 |
| 7167967 |
Memory module and memory-assist module |
Jan. 23, 2007 |
| 7154416 |
Adaptive control of codebook regeneration in data compression mechanisms |
Dec. 26, 2006 |
| 7149873 |
Methods and apparatus for a dual address space operating system |
Dec. 12, 2006 |
| 7149824 |
Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction |
Dec. 12, 2006 |
| 7149865 |
Memory allocation using mask-bit pattern to encode metadata within memory address |
Dec. 12, 2006 |
| 7145567 |
Bitstream format and reading and writing methods and apparatus therefor |
Dec. 5, 2006 |
| 7110437 |
Wireless communications systems and methods for direct memory access and buffering of digital signals for multiple user detection |
Sep. 19, 2006 |
| 7062632 |
Method for controlling a central processing unit for addressing in relation to a memory and controller |
Jun. 13, 2006 |
| 7035960 |
Method for increasing memory in a processor |
Apr. 25, 2006 |
| 7032100 |
Simple algorithmic cryptography engine |
Apr. 18, 2006 |
| 6993622 |
Bit level programming interface in a content addressable memory |
Jan. 31, 2006 |
| 6986004 |
FIFO memory with programmable data port widths |
Jan. 10, 2006 |
| 6970993 |
Architecture to relax memory performance requirements |
Nov. 29, 2005 |
| 6944637 |
Reduced size objects headers |
Sep. 13, 2005 |
| 6915396 |
Fast priority determination circuit with rotating priority |
Jul. 5, 2005 |
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