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Class Information
Number: 711/211
Name: Electrical computers and digital processing systems: memory > Address formation > Address multiplexing or address bus manipulation
Description: Subject matter including address bus
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7587571 |
Evaluation unit in an integrated circuit |
Sep. 8, 2009 |
| 7577818 |
Microprocessor program addressing arrangement having multiple independent complete address generators |
Aug. 18, 2009 |
| 7558944 |
Microcomputer |
Jul. 7, 2009 |
| 7549033 |
Dual edge command |
Jun. 16, 2009 |
| 7539811 |
Scaleable memory systems using third dimension memory |
May. 26, 2009 |
| 7539842 |
Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables |
May. 26, 2009 |
| 7502880 |
Apparatus and method for quad-pumped address bus |
Mar. 10, 2009 |
| 7493467 |
Address scrambling to simplify memory controller's address output multiplexer |
Feb. 17, 2009 |
| 7490190 |
Method and system for local memory addressing in single instruction, multiple data computer system |
Feb. 10, 2009 |
| 7490217 |
Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables |
Feb. 10, 2009 |
| 7451425 |
Determining controlling pins for a tile module of a programmable logic device |
Nov. 11, 2008 |
| 7444488 |
Method and programmable unit for bit field shifting |
Oct. 28, 2008 |
| 7436726 |
Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data |
Oct. 14, 2008 |
| 7414875 |
Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules |
Aug. 19, 2008 |
| 7406575 |
Method and system for storing data |
Jul. 29, 2008 |
| 7383416 |
Method for setting a second rank address from a first rank address in a memory module |
Jun. 3, 2008 |
| 7376809 |
Systems and methods for multi-frame control blocks |
May. 20, 2008 |
| 7376810 |
Integrated device with multiple reading and/or writing commands |
May. 20, 2008 |
| 7363466 |
Microcomputer |
Apr. 22, 2008 |
| 7360007 |
System including a segmentable, shared bus |
Apr. 15, 2008 |
| 7360040 |
Interleaver for iterative decoder |
Apr. 15, 2008 |
| 7356668 |
System and method for using address bits to form an index into secure memory |
Apr. 8, 2008 |
| 7350016 |
High speed DRAM cache architecture |
Mar. 25, 2008 |
| 7313610 |
Method and array for determining internet protocol addresses of a terminal array |
Dec. 25, 2007 |
| 7308552 |
Microcontroller |
Dec. 11, 2007 |
| 7293156 |
Distributed independent cache memory |
Nov. 6, 2007 |
| 7286436 |
High-density memory module utilizing low-density memory components |
Oct. 23, 2007 |
| 7268591 |
Decode structure with parallel rotation |
Sep. 11, 2007 |
| 7269709 |
Memory controller configurable to allow bandwidth/latency tradeoff |
Sep. 11, 2007 |
| 7243209 |
Apparatus and method for speeding up access time of a large register file with wrap capability |
Jul. 10, 2007 |
| 7231502 |
Method and system for storing data |
Jun. 12, 2007 |
| 7194519 |
System and method for administering a filer having a plurality of virtual filers |
Mar. 20, 2007 |
| 7149874 |
Memory hub bypass circuit and method |
Dec. 12, 2006 |
| 7136987 |
Memory configuration apparatus, systems, and methods |
Nov. 14, 2006 |
| 7126873 |
Method and system for expanding flash storage device capacity |
Oct. 24, 2006 |
| 7124223 |
Routability for memory devices |
Oct. 17, 2006 |
| 7111122 |
Access circuit with various access data units |
Sep. 19, 2006 |
| 7058756 |
Circuit for implementing special mode in packet-based semiconductor memory device |
Jun. 6, 2006 |
| 7032078 |
Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols |
Apr. 18, 2006 |
| 7000097 |
System and method for handling load and/or store operations in a superscalar microprocessor |
Feb. 14, 2006 |
| 6993622 |
Bit level programming interface in a content addressable memory |
Jan. 31, 2006 |
| 6982892 |
Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules |
Jan. 3, 2006 |
| 6963963 |
Multiprocessor system having a shared main memory accessible by all processor units |
Nov. 8, 2005 |
| 6961280 |
Techniques for implementing address recycling in memory circuits |
Nov. 1, 2005 |
| 6957316 |
Reader for standards and codes stored in electronic form |
Oct. 18, 2005 |
| 6948011 |
Alternate Register Mapping |
Sep. 20, 2005 |
| 6944694 |
Routability for memory devices |
Sep. 13, 2005 |
| 6915407 |
Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller |
Jul. 5, 2005 |
| 6912644 |
Method and apparatus to steer memory access operations in a virtual memory system |
Jun. 28, 2005 |
| 6910096 |
SDRAM with command decoder coupled to address registers |
Jun. 21, 2005 |
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