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Class Information
Number: 711/210
Name: Electrical computers and digital processing systems: memory > Address formation > Address mapping (e.g., conversion, translation) > Resolving conflict, coherency, or synonym problem
Description: Subject matter including compensating for situations when addresses map to the same location (e.g., synonym problems or alias addresses).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617379 |
Multi-hit control method for shared TLB in a multiprocessor system |
Nov. 10, 2009 |
| 7613669 |
Method and apparatus for storing pattern matching data and pattern matching method using the same |
Nov. 3, 2009 |
| 7594145 |
Improving performance of a processor having a defective cache |
Sep. 22, 2009 |
| 7552305 |
Dynamic and real-time management of memory |
Jun. 23, 2009 |
| 7536521 |
Computer storage device providing implicit detection of block liveness |
May. 19, 2009 |
| 7526628 |
Optimizing cache efficiency within application software |
Apr. 28, 2009 |
| 7523288 |
Dynamic fragment mapping |
Apr. 21, 2009 |
| 7523291 |
System and method for testing for memory address aliasing errors |
Apr. 21, 2009 |
| 7519792 |
Memory region access management |
Apr. 14, 2009 |
| 7512756 |
Performance improvement for block span replication |
Mar. 31, 2009 |
| 7467265 |
System and method for block conflict resolution within consistency interval marker based replication |
Dec. 16, 2008 |
| 7447845 |
Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality |
Nov. 4, 2008 |
| 7447844 |
Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule |
Nov. 4, 2008 |
| 7426625 |
Data processing system and computer program product for support of system memory addresses with holes |
Sep. 16, 2008 |
| 7424576 |
Parallel cachelets |
Sep. 9, 2008 |
| 7409525 |
Implicit locks in a shared virtual memory system |
Aug. 5, 2008 |
| 7398361 |
Combined buffer for snoop, store merging, load miss, and writeback operations |
Jul. 8, 2008 |
| 7395380 |
Selective snooping by snoop masters to locate updated data |
Jul. 1, 2008 |
| 7395405 |
Method and apparatus for supporting address translation in a virtual machine environment |
Jul. 1, 2008 |
| 7386643 |
Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions |
Jun. 10, 2008 |
| 7349348 |
Method and apparatus for determining a network topology in the presence of network address translation |
Mar. 25, 2008 |
| 7330961 |
Cache control method and processor system |
Feb. 12, 2008 |
| 7266652 |
System and method for managing data consistency between different data volumes on one or more data storage systems in a data storage environment |
Sep. 4, 2007 |
| 7251719 |
Recording medium playback apparatus |
Jul. 31, 2007 |
| 7240183 |
System and method for detecting instruction dependencies in multiple phases |
Jul. 3, 2007 |
| 7222221 |
Maintaining coherency of derived data in a computer system |
May. 22, 2007 |
| 7216201 |
Parallel cachelets |
May. 8, 2007 |
| 7177980 |
Cache storage system and method |
Feb. 13, 2007 |
| 7133995 |
Dynamic page conflict prediction for DRAM |
Nov. 7, 2006 |
| 7130983 |
System and method for reference count regeneration |
Oct. 31, 2006 |
| 7124276 |
Optimizing cache efficiency within application software |
Oct. 17, 2006 |
| 7117330 |
Synchronization techniques in a multithreaded environment |
Oct. 3, 2006 |
| 7096341 |
System and method for reference count regeneration |
Aug. 22, 2006 |
| 7089376 |
Reducing snoop response time for snoopers without copies of requested data via snoop filtering |
Aug. 8, 2006 |
| 7076628 |
Microprocessor memory space allocation management |
Jul. 11, 2006 |
| 7073047 |
Control chip and method for accelerating memory access |
Jul. 4, 2006 |
| 7020761 |
Blocking processing restrictions based on page indices |
Mar. 28, 2006 |
| 6993638 |
Memory access device and method using address translation history table |
Jan. 31, 2006 |
| 6983347 |
Dynamically managing saved processor soft states |
Jan. 3, 2006 |
| 6976129 |
Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture |
Dec. 13, 2005 |
| 6963964 |
Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses |
Nov. 8, 2005 |
| 6963962 |
Memory system for supporting multiple parallel accesses at very high frequencies |
Nov. 8, 2005 |
| 6963823 |
Programmatic design space exploration through validity filtering and quality filtering |
Nov. 8, 2005 |
| 6934827 |
Method and apparatus for avoiding cache line collisions between an object and corresponding object table entries |
Aug. 23, 2005 |
| 6925636 |
Method and apparatus for refining an alias set of address taken variables |
Aug. 2, 2005 |
| 6925464 |
Method and system for performing inserts and lookups in memory |
Aug. 2, 2005 |
| 6907505 |
Immediately available, statically allocated, full-logical-unit copy with a transient, snapshot-copy-like intermediate stage |
Jun. 14, 2005 |
| 6895492 |
Method of and apparatus for performing two-layer address translation |
May. 17, 2005 |
| 6854048 |
Speculative execution control with programmable indicator and deactivation of multiaccess recovery mechanism |
Feb. 8, 2005 |
| 6823434 |
System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state |
Nov. 23, 2004 |
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