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Class Information
Number: 711/167
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Access timing
Description: Subject matter including provisions for controlling or coordinating the sequence of operations that make up a memory
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620789 |
Out of order DRAM sequencer |
Nov. 17, 2009 |
| 7620788 |
Memory device sequencer and method supporting multiple memory device clock speeds |
Nov. 17, 2009 |
| 7620038 |
Using hot swap logic in a communication system |
Nov. 17, 2009 |
| 7617372 |
Avoiding copy on first write |
Nov. 10, 2009 |
| 7617354 |
Abbreviated burst data transfers for semiconductor memory |
Nov. 10, 2009 |
| 7613961 |
CPU register diagnostic testing |
Nov. 3, 2009 |
| 7613883 |
Memory device with mode-selectable prefetch and clock-to-core timing |
Nov. 3, 2009 |
| 7607579 |
Information processing apparatus |
Oct. 27, 2009 |
| 7606991 |
Dynamic clock switch mechanism for memories to improve performance |
Oct. 20, 2009 |
| 7603534 |
Synchronous flash memory with status burst output |
Oct. 13, 2009 |
| 7603533 |
System and method for data protection on a storage medium |
Oct. 13, 2009 |
| 7603512 |
Dynamic memory refresh controller, memory system including the same and method of controlling refresh of dynamic memory |
Oct. 13, 2009 |
| 7600091 |
Executing background writes to idle DIMMS |
Oct. 6, 2009 |
| 7600090 |
Microcontroller based flash memory digital controller system |
Oct. 6, 2009 |
| 7600078 |
Speculatively performing read transactions |
Oct. 6, 2009 |
| 7596707 |
System and method for efficient power throttling in multiprocessor chip |
Sep. 29, 2009 |
| 7596669 |
Apparatus and method for managing memory in a network switch |
Sep. 29, 2009 |
| 7594089 |
Smart memory based synchronization controller for a multi-threaded multiprocessor SoC |
Sep. 22, 2009 |
| 7594088 |
System and method for an asynchronous data buffer having buffer write and read pointers |
Sep. 22, 2009 |
| 7594072 |
Method and apparatus incorporating virtualization for data storage and protection |
Sep. 22, 2009 |
| 7590806 |
Filtering of transactional memory operations using associative tables |
Sep. 15, 2009 |
| 7590789 |
Optimizing clock crossing and data path latency |
Sep. 15, 2009 |
| 7587566 |
Realtime memory management via locking realtime threads and related data structures |
Sep. 8, 2009 |
| 7587547 |
Dynamic update adaptive idle timer |
Sep. 8, 2009 |
| 7587310 |
Sound processor architecture using single port memory unit |
Sep. 8, 2009 |
| 7586800 |
Memory timing apparatus and associated methods |
Sep. 8, 2009 |
| 7584335 |
Methods and arrangements for hybrid data storage |
Sep. 1, 2009 |
| 7581121 |
System for a memory device having a power down mode and method |
Aug. 25, 2009 |
| 7580465 |
Low speed access to DRAM |
Aug. 25, 2009 |
| 7577811 |
Memory controller for daisy chained self timed memory chips |
Aug. 18, 2009 |
| 7577049 |
Speculative sense enable tuning apparatus and associated methods |
Aug. 18, 2009 |
| 7574616 |
Memory device having a power down exit register |
Aug. 11, 2009 |
| 7574567 |
Monitoring processes in a non-uniform memory access (NUMA) computer system |
Aug. 11, 2009 |
| 7574548 |
Dynamic data transfer control method and apparatus for shared SMP computer systems |
Aug. 11, 2009 |
| 7571330 |
System and module including a memory device having a power down mode |
Aug. 4, 2009 |
| 7571297 |
Data invalid signal for non-deterministic latency in a memory system |
Aug. 4, 2009 |
| 7571296 |
Memory controller-adaptive 1T/2T timing control |
Aug. 4, 2009 |
| 7571283 |
Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch |
Aug. 4, 2009 |
| 7571279 |
Accessing a disk drive at multiple speeds |
Aug. 4, 2009 |
| 7562185 |
Accessing a storage medium using dynamic read statistics |
Jul. 14, 2009 |
| 7561529 |
Optimizing the speed of an FC-AL switch domain in a data storage network |
Jul. 14, 2009 |
| 7558934 |
Data storage unit, data storage controlling apparatus and method, and data storage controlling program |
Jul. 7, 2009 |
| 7558932 |
Semiconductor memory device and method for operating the same |
Jul. 7, 2009 |
| 7558924 |
Systems and methods for accessing memory cells |
Jul. 7, 2009 |
| 7558918 |
System for handling streaming information using a plurality of reader modules by enumerating output pins and associated streams of information |
Jul. 7, 2009 |
| 7555670 |
Clocking architecture using a bidirectional clock port |
Jun. 30, 2009 |
| 7552303 |
Memory pacing |
Jun. 23, 2009 |
| 7552302 |
Ordering operation |
Jun. 23, 2009 |
| 7552301 |
Information processing apparatus and memory access arranging method |
Jun. 23, 2009 |
| 7549033 |
Dual edge command |
Jun. 16, 2009 |
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