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Class Information
Number: 711/163
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Control technique > Access limiting
Description: Subject matter wherein memory
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6240531 |
System and method for computer operating system protection |
May. 29, 2001 |
| 6230244 |
Memory device with read access controlled by code |
May. 8, 2001 |
| 6226709 |
Memory refresh control system |
May. 1, 2001 |
| 6223263 |
Method and apparatus for locking and unlocking a memory region |
Apr. 24, 2001 |
| 6223268 |
System and method for writing specific bytes in a wide-word memory |
Apr. 24, 2001 |
| 6216183 |
Apparatus and method for securing information entered upon an input device coupled to a universal serial bus |
Apr. 10, 2001 |
| 6216207 |
Performance monitoring storage module for storing performance management data |
Apr. 10, 2001 |
| 6216211 |
Method and apparatus for accessing mirrored logical volumes |
Apr. 10, 2001 |
| 6216212 |
Scaleable method for maintaining and making consistent updates to caches |
Apr. 10, 2001 |
| 6212608 |
Method and apparatus for thread synchronization in an object-based system |
Apr. 3, 2001 |
| 6209069 |
Method and apparatus using volatile lock architecture for individual block locking on flash memory |
Mar. 27, 2001 |
| 6202154 |
Data transfer controller, microcomputer and data processing system |
Mar. 13, 2001 |
| 6199148 |
Method and apparatus for preventing unauthorized use in systems having alternative control for avoiding defect areas on recording media |
Mar. 6, 2001 |
| 6195732 |
Storage device capacity management |
Feb. 27, 2001 |
| 6192455 |
Apparatus and method for preventing access to SMRAM space through AGP addressing |
Feb. 20, 2001 |
| 6189078 |
System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency |
Feb. 13, 2001 |
| 6182159 |
System for detachably connecting memory cards which provide memory specified by predetermined range of addresses registered in list and updating list independent of the I/O operation |
Jan. 30, 2001 |
| 6182199 |
System and method for granting permission to modify a memory area |
Jan. 30, 2001 |
| 6178550 |
Mechanism for optimizing location of machine-dependent code |
Jan. 23, 2001 |
| 6175881 |
Microcontroller having a memory, a dedicated multitask memory, and switching circuit for selectively connecting the multitask memory to the internal or external bus |
Jan. 16, 2001 |
| 6175951 |
Method for fabricating a customer-configured integrated circuit and customer-configured integrated circuit for exclusive use by a customer background of the invention |
Jan. 16, 2001 |
| 6173378 |
Method for ordering a request for access to a system memory using a reordering buffer or FIFO |
Jan. 9, 2001 |
| 6167494 |
Method and system for recovering from operating system failure |
Dec. 26, 2000 |
| 6160501 |
Storing packet data |
Dec. 12, 2000 |
| 6154814 |
Cache device that reduces waiting time necessary for a given subsequent request to gain access to the cache |
Nov. 28, 2000 |
| 6154818 |
System and method of controlling access to privilege partitioned address space for a model specific register file |
Nov. 28, 2000 |
| 6154819 |
Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks |
Nov. 28, 2000 |
| 6148384 |
Decoupled serial memory access with passkey protected memory areas |
Nov. 14, 2000 |
| 6148385 |
High speed digital electronic memory having a read and write in one cycle |
Nov. 14, 2000 |
| 6148441 |
Method for reprogramming flash ROM in a personal computer implementing an EISA bus system |
Nov. 14, 2000 |
| 6145080 |
Method for safely transferring data and applications onto a chipcard |
Nov. 7, 2000 |
| 6141736 |
Arrangement with master and slave units |
Oct. 31, 2000 |
| 6141734 |
Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol |
Oct. 31, 2000 |
| 6138220 |
Method and device for the predictive reading of a memory |
Oct. 24, 2000 |
| 6134549 |
Client/server computer system having personalizable and securable views of database data |
Oct. 17, 2000 |
| 6134627 |
Thread synchronization in a computer controlled by an object-based program |
Oct. 17, 2000 |
| 6134636 |
Method and apparatus for storing data in a memory array |
Oct. 17, 2000 |
| 6122716 |
System and method for authenticating a computer memory |
Sep. 19, 2000 |
| 6119210 |
Device for the protection of stored data using a time delay circuit |
Sep. 12, 2000 |
| 6112282 |
Apparatus for atomic locking-accessing-unlocking of a shared resource |
Aug. 29, 2000 |
| 6108235 |
Memory device |
Aug. 22, 2000 |
| 6108748 |
System and method for on-line, real time, data migration |
Aug. 22, 2000 |
| 6105085 |
Lock mechanism for shared resources having associated data structure stored in common memory include a lock portion and a reserve portion |
Aug. 15, 2000 |
| 6105118 |
System and method for selecting which data copy to read in an information handling system |
Aug. 15, 2000 |
| 6101573 |
Bit line and/or match line partitioned content addressable memory |
Aug. 8, 2000 |
| 6101584 |
Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory |
Aug. 8, 2000 |
| 6101586 |
Memory access control circuit |
Aug. 8, 2000 |
| 6101587 |
Data protection circuit for semiconductor memory device |
Aug. 8, 2000 |
| 6101588 |
Device level busy arrangement for mass storage subsystem including a plurality of devices |
Aug. 8, 2000 |
| 6098133 |
Secure bus arbiter interconnect arrangement |
Aug. 1, 2000 |
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