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Class Information
Number: 711/155
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Control technique > Read-modify-write (rmw)
Description: Subject matter including provisions for performing an access operation where the contents of a given memory
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5938739 |
Memory controller including write posting queues, bus read control logic, and a data contents counter |
Aug. 17, 1999 |
| 5937199 |
User programmable interrupt mask with timeout for enhanced resource locking efficiency |
Aug. 10, 1999 |
| 5933595 |
Computer apparatus having electrically rewritable nonvolatile memory, and nonvolatile semiconductor memory |
Aug. 3, 1999 |
| 5925139 |
Microcomputer capable of preventing writing errors in a non-volatile memory |
Jul. 20, 1999 |
| 5920714 |
System and method for distributed multiprocessor communications |
Jul. 6, 1999 |
| 5909696 |
Method and apparatus for caching system management mode information with other information |
Jun. 1, 1999 |
| 5909699 |
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency |
Jun. 1, 1999 |
| 5873122 |
Memory system performing fast access to a memory location by omitting transfer of a redundant address |
Feb. 16, 1999 |
| 5867734 |
Multiple-reader multiple-writer queue for a computer system |
Feb. 2, 1999 |
| 5860102 |
Cache memory circuit |
Jan. 12, 1999 |
| 5838960 |
Apparatus for performing an atomic add instructions |
Nov. 17, 1998 |
| 5802586 |
Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor |
Sep. 1, 1998 |
| 5802587 |
Memory controller adapted for rapid block access operations |
Sep. 1, 1998 |
| 5802579 |
System and method for simultaneously reading and writing data in a random access memory |
Sep. 1, 1998 |
| 5802548 |
Software programmable edge delay for SRAM write enable signals on dual purpose cache controllers |
Sep. 1, 1998 |
| 5787486 |
Bus protocol for locked cycle cache hit |
Jul. 28, 1998 |
| 5787460 |
Disk array apparatus that only calculates new parity after a predetermined number of write requests |
Jul. 28, 1998 |
| 5787240 |
Printer control apparatus converting video data from an external host to video data for a printer |
Jul. 28, 1998 |
| 5761731 |
Method and apparatus for performing atomic transactions in a shared memory multi processor system |
Jun. 2, 1998 |
| 5751999 |
Processor and data memory for outputting and receiving data on different buses for storage in the same location |
May. 12, 1998 |
| 5751574 |
Method for loading software in communication systems with non-redundant, decentralized equipment |
May. 12, 1998 |
| 5740401 |
Multiprocessor system having a processor invalidating operand cache when lock-accessing |
Apr. 14, 1998 |
| 5729711 |
Data driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writings |
Mar. 17, 1998 |
| 5712880 |
Traceback-performing apparatus in viterbi decoder |
Jan. 27, 1998 |
| 5706464 |
Method and system for achieving atomic memory references in a multilevel cache data processing system |
Jan. 6, 1998 |
| 5701501 |
Apparatus and method for executing an atomic instruction |
Dec. 23, 1997 |
| 5696933 |
Apparatus for controlling data writing into a disk array system including a data length detecting unit and a writing mode selector |
Dec. 9, 1997 |
| 5690435 |
Serial printing apparatus with sentence memory and display |
Nov. 25, 1997 |
| 5687353 |
Merging data using a merge code from a look-up table and performing ECC generation on the merged data |
Nov. 11, 1997 |
| 5668967 |
Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency |
Sep. 16, 1997 |
| 5666515 |
Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try t |
Sep. 9, 1997 |
| 5613088 |
Raid system including first and second read/write heads for each disk drive |
Mar. 18, 1997 |
| 5594877 |
System for transferring data onto buses having different widths |
Jan. 14, 1997 |
| 5583985 |
Graphic display processing apparatus for improving speed and efficiency of a window system |
Dec. 10, 1996 |
| 5579505 |
Memory access system and method for granting or preventing atomic or nonatomic memory access requests to shared memory regions |
Nov. 26, 1996 |
| 5574884 |
DRAM control circuit |
Nov. 12, 1996 |
| 5572702 |
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency |
Nov. 5, 1996 |
| 5553267 |
Method and apparatus for coordinating access to and modifying multiple element data objects in a shared memory |
Sep. 3, 1996 |
| 5542084 |
Method and apparatus for executing an atomic read-modify-write instruction |
Jul. 30, 1996 |
| 5535365 |
Method and apparatus for locking shared memory locations in multiprocessing systems |
Jul. 9, 1996 |
| 5526510 |
Method and apparatus for implementing a single clock cycle line replacement in a data cache unit |
Jun. 11, 1996 |
| 5526128 |
Image producing apparatus with memory unit having an image memory area of changeable storage capacity |
Jun. 11, 1996 |
| 5506977 |
Method and controller for minimizing reads during partial stripe write operations to a disk drive |
Apr. 9, 1996 |
| 5499356 |
Method and apparatus for a multiprocessor resource lockout instruction |
Mar. 12, 1996 |
| 5491811 |
Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory |
Feb. 13, 1996 |
| 5485594 |
Apparatus and method using an atomic fetch and add for establishing temporary ownership of a common system resource in a multiprocessor data processing system |
Jan. 16, 1996 |
| 5485588 |
Memory array based data reorganizer |
Jan. 16, 1996 |
| 5459842 |
System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory |
Oct. 17, 1995 |
| 5452429 |
Error correction code on add-on cards for writing portions of data words |
Sep. 19, 1995 |
| 5432912 |
Method and channel apparatus for rearranging received data in order of generation of addresses |
Jul. 11, 1995 |
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