| Patent Number |
Title Of Patent |
Date Issued |
| 6557086 |
Memory write and read control |
Apr. 29, 2003 |
| 6553465 |
Multiprocessor system with distributed shared memory having hot plug function for main memories |
Apr. 22, 2003 |
| 6526482 |
Method of and apparatus for tracking appended data on storage medium |
Feb. 25, 2003 |
| 6493803 |
Direct memory access controller with channel width configurability support |
Dec. 10, 2002 |
| 6480928 |
Memory rewriting system for vehicle controller |
Nov. 12, 2002 |
| 6463503 |
Method and system for increasing concurrency during staging and destaging in a log structured array |
Oct. 8, 2002 |
| 6457104 |
System and method for recycling stale memory content in compressed memory systems |
Sep. 24, 2002 |
| 6415364 |
High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems |
Jul. 2, 2002 |
| 6405293 |
Selectively accessible memory banks for operating in alternately reading or writing modes of operation |
Jun. 11, 2002 |
| 6389517 |
Maintaining snoop traffic throughput in presence of an atomic operation a first port for a first queue tracks cache requests and a second port for a second queue snoops that have yet to be fil |
May. 14, 2002 |
| 6370625 |
Method and apparatus for lock synchronization in a microprocessor system |
Apr. 9, 2002 |
| 6370631 |
Memory controller including compression/decompression capabilities for improved data access |
Apr. 9, 2002 |
| 6356991 |
Programmable address translation system |
Mar. 12, 2002 |
| 6353877 |
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write |
Mar. 5, 2002 |
| 6347360 |
Apparatus and method for preventing cache data eviction during an atomic operation |
Feb. 12, 2002 |
| 6343343 |
Disk arrays using non-standard sector sizes |
Jan. 29, 2002 |
| 6339813 |
Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory |
Jan. 15, 2002 |
| 6336164 |
Method and system for preventing deadlock in a log structured array |
Jan. 1, 2002 |
| 6332181 |
Recovery mechanism for L1 data cache parity errors |
Dec. 18, 2001 |
| 6295578 |
Cascaded removable media data storage system |
Sep. 25, 2001 |
| 6289065 |
FIFO status indicator |
Sep. 11, 2001 |
| 6279088 |
Memory device with multiple processors having parallel access to the same memory area |
Aug. 21, 2001 |
| 6269424 |
Disk array device with selectable method for generating redundant data |
Jul. 31, 2001 |
| 6266743 |
Method and system for providing an eviction protocol within a non-uniform memory access system |
Jul. 24, 2001 |
| 6260103 |
Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers |
Jul. 10, 2001 |
| 6230237 |
Content addressable memory with an internally-timed write operation |
May. 8, 2001 |
| 6230235 |
Address lookup DRAM aging |
May. 8, 2001 |
| 6226017 |
Methods and apparatus for improving read/modify/write operations |
May. 1, 2001 |
| 6223259 |
Reducing read cycle of memory read request for data to be partially modified by a pending write request |
Apr. 24, 2001 |
| 6219745 |
System and method for entering a stream read buffer mode to store non-cacheable or block data |
Apr. 17, 2001 |
| 6173381 |
Memory controller including embedded data compression and decompression engines |
Jan. 9, 2001 |
| 6170047 |
System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities |
Jan. 2, 2001 |
| 6154807 |
Memory system performing fast access to a memory location by omitting the transfer of a redundant address |
Nov. 28, 2000 |
| 6148300 |
Hybrid queue and backoff computer resource lock featuring different spin speeds corresponding to multiple-states |
Nov. 14, 2000 |
| 6128711 |
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes |
Oct. 3, 2000 |
| 6112255 |
Method and means for managing disk drive level logic and buffer modified access paths for enhanced raid array data rebuild and write update operations |
Aug. 29, 2000 |
| 6105114 |
Two-dimensional array transposition circuit reading two-dimensional array in an order different from that for writing |
Aug. 15, 2000 |
| 6078999 |
Recovering from a failure using a transaction table in connection with shadow copy transaction processing |
Jun. 20, 2000 |
| 6073158 |
System and method for processing multiple received signal sources |
Jun. 6, 2000 |
| 6073219 |
Semiconductor memory device with high speed read-modify-write function |
Jun. 6, 2000 |
| 6073211 |
Method and system for memory updates within a multiprocessor data processing system |
Jun. 6, 2000 |
| 6067635 |
Preservation of data integrity in a raid storage device |
May. 23, 2000 |
| 6061783 |
Method and apparatus for manipulation of bit fields directly in a memory source |
May. 9, 2000 |
| 6032233 |
Storage array allowing for multiple, simultaneous write accesses |
Feb. 29, 2000 |
| 6021463 |
Method and means for efficiently managing update writes and fault tolerance in redundancy groups of addressable ECC-coded sectors in a DASD storage subsystem |
Feb. 1, 2000 |
| 6018791 |
Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states |
Jan. 25, 2000 |
| 5996052 |
Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array |
Nov. 30, 1999 |
| 5987572 |
Method and apparatus employing a dynamic encryption interface between a processor and a memory |
Nov. 16, 1999 |
| 5974514 |
Controlling SDRAM memory by using truncated burst read-modify-write memory operations |
Oct. 26, 1999 |
| 5963960 |
Method and apparatus for queuing updates in a computer system |
Oct. 5, 1999 |
