| Patent Number |
Title Of Patent |
Date Issued |
| 5922057 |
Method for multiprocessor system of controlling a dynamically expandable shared queue in which ownership of a queue entry by a processor is indicated by a semaphore |
Jul. 13, 1999 |
| 5920893 |
Storage control and computer system using the same |
Jul. 6, 1999 |
| 5918229 |
Structured data storage using globally addressable memory |
Jun. 29, 1999 |
| 5918248 |
Shared memory control algorithm for mutual exclusion and rollback |
Jun. 29, 1999 |
| 5915262 |
Cache system and method using tagged cache lines for matching cache strategy to I/O application |
Jun. 22, 1999 |
| 5911149 |
Apparatus and method for implementing a programmable shared memory with dual bus architecture |
Jun. 8, 1999 |
| 5906658 |
Message queuing on a data storage system utilizing message queuing in intended recipient's queue |
May. 25, 1999 |
| 5903913 |
Method and apparatus for storage system management in a multi-host environment |
May. 11, 1999 |
| 5900018 |
Processor-implemented method of controlling data access to shared resource via exclusive access control write-cache |
May. 4, 1999 |
| 5900020 |
Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency |
May. 4, 1999 |
| 5901328 |
System for transferring data between main computer multiport memory and external device in parallel system utilizing memory protection scheme and changing memory protection area |
May. 4, 1999 |
| 5897635 |
Single access to common user/application information |
Apr. 27, 1999 |
| 5897658 |
Method and apparatus for protecting portions of memory by providing access requests to a communications area for processing by a hidden server |
Apr. 27, 1999 |
| 5897664 |
Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies |
Apr. 27, 1999 |
| 5898883 |
Memory access mechanism for a parallel processing computer system with distributed shared memory |
Apr. 27, 1999 |
| 5895484 |
Method and system for speculatively accessing cache memory data within a multiprocessor data-processing system using a cache controller |
Apr. 20, 1999 |
| 5895491 |
Apparatus and method for writing an item to a line in a memory table shared by multiple processors |
Apr. 20, 1999 |
| 5895492 |
Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system |
Apr. 20, 1999 |
| 5895493 |
Method and apparatus for storage of multiple host storage management information on a storage subsystem |
Apr. 20, 1999 |
| 5893098 |
System and method for obtaining and collating survey information from a plurality of computer users |
Apr. 6, 1999 |
| 5893144 |
Hybrid NUMA COMA caching system and methods for selecting between the caching modes |
Apr. 6, 1999 |
| 5893156 |
Lock control apparatus and method including controlling means for setting a lock variable status |
Apr. 6, 1999 |
| 5893159 |
Methods and apparatus for managing scratchpad memory in a multiprocessor data processing system |
Apr. 6, 1999 |
| 5893166 |
Addressing method and system for sharing a large memory address space using a system space global memory section |
Apr. 6, 1999 |
| 5889948 |
Apparatus and method for inserting an address in a data stream through a FIFO buffer |
Mar. 30, 1999 |
| 5890007 |
Multi-cluster parallel processing computer system |
Mar. 30, 1999 |
| 5890013 |
Paged memory architecture for a single chip multi-processor with physical memory pages that are swapped without latency |
Mar. 30, 1999 |
| 5890217 |
Coherence apparatus for cache of multiprocessor |
Mar. 30, 1999 |
| 5887188 |
Multiprocessor system providing enhanced efficiency of accessing page mode memory by master processor |
Mar. 23, 1999 |
| 5875470 |
Multi-port multiple-simultaneous-access DRAM chip |
Feb. 23, 1999 |
| 5872998 |
System using a primary bridge to recapture shared portion of a peripheral memory of a peripheral device to provide plug and play capability |
Feb. 16, 1999 |
| 5873116 |
Method and apparatus for controlling access to data structures without the use of locks |
Feb. 16, 1999 |
| 5870573 |
Transistor switch used to isolate bus devices and/or translate bus voltage levels |
Feb. 9, 1999 |
| 5867682 |
High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations |
Feb. 2, 1999 |
| 5867683 |
Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations |
Feb. 2, 1999 |
| 5860108 |
Method and clustered multi-processor system for controlling a clock phase for clusters |
Jan. 12, 1999 |
| 5860109 |
Methods and apparatus for a coherence transformer for connecting computer system coherence domains |
Jan. 12, 1999 |
| 5860110 |
Conference maintenance method for cache memories in multi-processor system triggered by a predetermined synchronization point and a predetermined condition |
Jan. 12, 1999 |
| 5860115 |
Requesting a dump of information stored within a coupling facility, in which the dump includes serviceability information from an operating system that lost communication with the coupling fac |
Jan. 12, 1999 |
| 5860126 |
Controlling shared memory access ordering in a multi-processing system using an acquire/release consistency model |
Jan. 12, 1999 |
| 5848411 |
Method for distributedly processing a plurality of jobs in a data processing system |
Dec. 8, 1998 |
| 5835927 |
Special test modes for a page buffer shared resource in a memory device |
Nov. 10, 1998 |
| 5832216 |
Network adapter having single ported memory which is accessible by network and peripheral bus on a time division multiplexed (TDM) basis |
Nov. 3, 1998 |
| 5828821 |
Checkpoint restart method and apparatus utilizing multiple log memories |
Oct. 27, 1998 |
| 5829041 |
Method and apparatus for managing single virtual space suitable for distributed processing |
Oct. 27, 1998 |
| 5829042 |
Prefetch operation for network peripheral device having shared memory |
Oct. 27, 1998 |
| 5829052 |
Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system |
Oct. 27, 1998 |
| 5822601 |
Apparatus to allow a CPU to control the relocation of code blocks for other CPUs |
Oct. 13, 1998 |
| 5822766 |
Main memory interface for high speed data transfer |
Oct. 13, 1998 |
| 5812816 |
System and method for transferring data between memories of different types occupying a single real address space using a dedicated memory transfer bus |
Sep. 22, 1998 |
