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Class Information
Number: 711/147
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Shared memory area
Description: Subject matter wherein at least a portion of the memory
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6970984 |
Digital signal processor and modem using the same |
Nov. 29, 2005 |
| 6968386 |
System for transferring data files between a user workstation and web server |
Nov. 22, 2005 |
| 6968432 |
Method and system for altering a sequence number assignment pattern while preserving integrity and high concurrency in a multi-system shared disk environment |
Nov. 22, 2005 |
| 6963946 |
Descriptor management systems and methods for transferring data between a host and a peripheral |
Nov. 8, 2005 |
| 6961825 |
Cache coherency mechanism using arbitration masks |
Nov. 1, 2005 |
| 6954210 |
Display data generating device |
Oct. 11, 2005 |
| 6954824 |
Method, system, and program for determining a configuration of a logical array including a plurality of storage devices |
Oct. 11, 2005 |
| 6952722 |
Method and system using peer mapping system call to map changes in shared memory to all users of the shared memory |
Oct. 4, 2005 |
| 6952755 |
Control device for file resources in a network |
Oct. 4, 2005 |
| 6952761 |
Bus interface selection by page table attributes |
Oct. 4, 2005 |
| 6950906 |
System for and method of operating a cache |
Sep. 27, 2005 |
| 6950912 |
Memory manager for a common memory |
Sep. 27, 2005 |
| 6947050 |
Method of implementing an accelerated graphics/port for a multiple memory controller computer system |
Sep. 20, 2005 |
| 6948005 |
Peripheral device for programmable controller |
Sep. 20, 2005 |
| 6948010 |
Method and apparatus for efficiently moving portions of a memory block |
Sep. 20, 2005 |
| 6948011 |
Alternate Register Mapping |
Sep. 20, 2005 |
| 6948045 |
Providing a register file memory with local addressing in a SIMD parallel processor |
Sep. 20, 2005 |
| 6944722 |
Method and system for postmortem identification of falsely shared memory objects |
Sep. 13, 2005 |
| 6944723 |
Data processing device for processing data accessed by a buffer manager, and interface device |
Sep. 13, 2005 |
| 6944726 |
Distributed background track processing |
Sep. 13, 2005 |
| 6941391 |
Fencepost descriptor caching mechanism and method therefor |
Sep. 6, 2005 |
| 6941424 |
System, method, and computer program product for high speed DMA-based backplane messaging |
Sep. 6, 2005 |
| 6941433 |
Systems and methods for memory read response latency detection |
Sep. 6, 2005 |
| 6938129 |
Distributed memory module cache |
Aug. 30, 2005 |
| 6938143 |
Dynamically adaptive buffer mechanism |
Aug. 30, 2005 |
| 6938252 |
Hardware-assisted method for scheduling threads using data cache locality |
Aug. 30, 2005 |
| 6934815 |
Method and apparatus used for data communication between processors, and data processing apparatus |
Aug. 23, 2005 |
| 6931497 |
Shared memory management utilizing a free list of buffer indices |
Aug. 16, 2005 |
| 6931505 |
Distributed memory module cache command formatting |
Aug. 16, 2005 |
| 6930634 |
Shared memory architecture in GPS signal processing |
Aug. 16, 2005 |
| 6928027 |
Virtual dual-port synchronous RAM architecture |
Aug. 9, 2005 |
| 6928523 |
Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocesso |
Aug. 9, 2005 |
| 6928531 |
Linear and non-linear object management |
Aug. 9, 2005 |
| 6925532 |
Broadcast system in disk array controller |
Aug. 2, 2005 |
| 6925634 |
Method for maintaining cache coherency in software in a shared memory system |
Aug. 2, 2005 |
| 6922757 |
Flexible and adaptive read and write storage system architecture |
Jul. 26, 2005 |
| 6920529 |
Transferring data between cache memory and a media access controller |
Jul. 19, 2005 |
| 6918014 |
Dynamic distributed data system and method |
Jul. 12, 2005 |
| 6918015 |
Scalable directory based cache coherence protocol |
Jul. 12, 2005 |
| 6915389 |
Storage system, disk control cluster, and its increase method |
Jul. 5, 2005 |
| 6915391 |
Support for single-node quorum in a two-node nodeset for a shared disk parallel file system |
Jul. 5, 2005 |
| 6915392 |
Optimizing memory usage by vtable cloning |
Jul. 5, 2005 |
| 6915402 |
Method and system for creating secure address space using hardware memory router |
Jul. 5, 2005 |
| 6912553 |
Virtual machine memory management |
Jun. 28, 2005 |
| 6912621 |
Method and apparatus for updating data in mass storage subsystem using emulated shared memory |
Jun. 28, 2005 |
| 6912716 |
Maximized data space in shared memory between processors |
Jun. 28, 2005 |
| 6907477 |
Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors |
Jun. 14, 2005 |
| 6907483 |
Data storage system having dummy printed circuit boards with jumpers |
Jun. 14, 2005 |
| 6907508 |
Structure and method for managing available memory resources |
Jun. 14, 2005 |
| 6907601 |
Method and apparatus for inserting more than one allocation instruction within a routine |
Jun. 14, 2005 |
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