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Class Information
Number: 711/142
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency > Write-through
Description: Subject matter where, as contents of the cache are changed, the changes are also posted to main memory
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7606978 |
Multi-node computer system implementing global access state dependent transactions |
Oct. 20, 2009 |
| 7581042 |
I/O hub resident cache line monitor and device register update |
Aug. 25, 2009 |
| 7555610 |
Cache memory and control method thereof |
Jun. 30, 2009 |
| 7536428 |
Concurrent read and write access to a linked list where write process updates the linked list by swapping updated version of the linked list with internal list |
May. 19, 2009 |
| 7523268 |
Reducing number of rejected snoop requests by extending time to respond to snoop request |
Apr. 21, 2009 |
| 7502903 |
Method and apparatus for managing data storage systems |
Mar. 10, 2009 |
| 7484044 |
Method and apparatus for joint cache coherency states in multi-interface caches |
Jan. 27, 2009 |
| 7484046 |
Reducing number of rejected snoop requests by extending time to respond to snoop request |
Jan. 27, 2009 |
| 7478202 |
Using the message fabric to maintain cache coherency of local caches of global memory |
Jan. 13, 2009 |
| 7475191 |
Processor, data processing system and method for synchronizing access to data in shared memory |
Jan. 6, 2009 |
| 7472229 |
Bus controller initiated write-through mechanism |
Dec. 30, 2008 |
| 7472230 |
Preemptive write back controller |
Dec. 30, 2008 |
| 7447812 |
Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files |
Nov. 4, 2008 |
| 7386681 |
Reducing number of rejected snoop requests by extending time to respond to snoop request |
Jun. 10, 2008 |
| 7386682 |
Reducing number of rejected snoop requests by extending time to respond to snoop request |
Jun. 10, 2008 |
| 7376789 |
Wide-port context cache apparatus, systems, and methods |
May. 20, 2008 |
| 7376799 |
System for reducing the latency of exclusive read requests in a symmetric multi-processing system |
May. 20, 2008 |
| 7360031 |
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces |
Apr. 15, 2008 |
| 7356651 |
Data-aware cache state machine |
Apr. 8, 2008 |
| 7340568 |
Reducing number of rejected snoop requests by extending time to respond to snoop request |
Mar. 4, 2008 |
| 7340563 |
Data transmission device having the shape of a standard 3.5'' disk |
Mar. 4, 2008 |
| 7263580 |
Cache flush based on checkpoint timer |
Aug. 28, 2007 |
| 7254686 |
Switching between mirrored and non-mirrored volumes |
Aug. 7, 2007 |
| 7237069 |
Arrangement and method for update of configuration cache data |
Jun. 26, 2007 |
| 7234028 |
Power/performance optimized cache using memory write prevention through write snarfing |
Jun. 19, 2007 |
| 7233880 |
Adaptive cache algorithm for temperature sensitive memory |
Jun. 19, 2007 |
| 7231497 |
Merging write-back and write-through cache policies |
Jun. 12, 2007 |
| 7228385 |
Processor, data processing system and method for synchronizing access to data in shared memory |
Jun. 5, 2007 |
| 7219197 |
Cache memory, processor and cache control method |
May. 15, 2007 |
| 7216202 |
Method and apparatus for supporting one or more servers on a single semiconductor chip |
May. 8, 2007 |
| 7200717 |
Processor, data processing system and method for synchronizing access to data in shared memory |
Apr. 3, 2007 |
| 7197604 |
Processor, data processing system and method for synchronzing access to data in shared memory |
Mar. 27, 2007 |
| 7194587 |
Localized cache block flush instruction |
Mar. 20, 2007 |
| 7185029 |
Method and apparatus for maintaining, and updating in-memory copies of the first and second pointers to reference the new versions of the first and second control structures that indicate avai |
Feb. 27, 2007 |
| 7177987 |
System and method for responses between different cache coherency protocols |
Feb. 13, 2007 |
| 7162625 |
System and method for testing memory during boot operation idle periods |
Jan. 9, 2007 |
| 7159079 |
Multiprocessor system |
Jan. 2, 2007 |
| 7136969 |
Using the message fabric to maintain cache coherency of local caches of global memory |
Nov. 14, 2006 |
| 7120752 |
Multi-processor computer system with cache-flushing system using memory recall |
Oct. 10, 2006 |
| 7103722 |
Cache configuration for compressed memory systems |
Sep. 5, 2006 |
| 7082500 |
Optimized high bandwidth cache coherence mechanism |
Jul. 25, 2006 |
| 7076613 |
Cache line pre-load and pre-own based on cache coherence speculation |
Jul. 11, 2006 |
| 7076614 |
System and method for optimizing bus bandwidth utilization by grouping cache write-backs |
Jul. 11, 2006 |
| 7039908 |
Unification-based points-to-analysis using multilevel typing |
May. 2, 2006 |
| 7003631 |
System having address-based intranode coherency and data-based internode coherency |
Feb. 21, 2006 |
| 6996683 |
Cache coherency in a multi-processor system |
Feb. 7, 2006 |
| 6993631 |
L2 cache maintaining local ownership of remote coherency blocks |
Jan. 31, 2006 |
| 6988170 |
Scalable architecture based on single-chip multiprocessing |
Jan. 17, 2006 |
| 6983348 |
Methods and apparatus for cache intervention |
Jan. 3, 2006 |
| 6981097 |
Token based cache-coherence protocol |
Dec. 27, 2005 |
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