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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7209932 |
Method, system, and program for allocating tasks to a plurality of processors |
Apr. 24, 2007 |
| 7206879 |
Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems |
Apr. 17, 2007 |
| 7200721 |
Verification of memory operations by multiple processors to a shared memory |
Apr. 3, 2007 |
| 7200720 |
System and method for efficiently performing memory intensive computations including a bidirectional synchronization mechanism for maintaining consistency of data |
Apr. 3, 2007 |
| 7200717 |
Processor, data processing system and method for synchronizing access to data in shared memory |
Apr. 3, 2007 |
| 7197605 |
Allocating cache lines |
Mar. 27, 2007 |
| 7197604 |
Processor, data processing system and method for synchronzing access to data in shared memory |
Mar. 27, 2007 |
| 7194587 |
Localized cache block flush instruction |
Mar. 20, 2007 |
| 7194586 |
Method and apparatus for implementing cache state as history of read/write shared data |
Mar. 20, 2007 |
| 7194585 |
Coherency controller management of transactions |
Mar. 20, 2007 |
| 7181576 |
Method for synchronizing a cache memory with a main memory |
Feb. 20, 2007 |
| 7174431 |
Mechanism for resolving ambiguous invalidates in a computer system |
Feb. 6, 2007 |
| 7174430 |
Bandwidth reduction technique using cache-to-cache transfer prediction in a snooping-based cache-coherent cluster of multiprocessing nodes |
Feb. 6, 2007 |
| 7174429 |
Method for extending the local memory address space of a processor |
Feb. 6, 2007 |
| 7174417 |
Buffer allocation method supporting detection-based and avoidance-based consistency maintenance policies in a shared disk-based multi-database management system |
Feb. 6, 2007 |
| 7171521 |
Coherent shared memory processing system |
Jan. 30, 2007 |
| 7167957 |
Mechanism for handling explicit writeback in a cache coherent multi-node architecture |
Jan. 23, 2007 |
| 7167956 |
Avoiding inconsistencies between multiple translators in an object-addressed memory hierarchy |
Jan. 23, 2007 |
| 7167955 |
System and method for testing and initializing directory store memory |
Jan. 23, 2007 |
| 7165149 |
Mechanism for starvation avoidance while maintaining cache consistency in computer systems |
Jan. 16, 2007 |
| 7162625 |
System and method for testing memory during boot operation idle periods |
Jan. 9, 2007 |
| 7162590 |
Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion |
Jan. 9, 2007 |
| 7162589 |
Methods and apparatus for canceling a memory data fetch |
Jan. 9, 2007 |
| 7159079 |
Multiprocessor system |
Jan. 2, 2007 |
| 7155577 |
Optimistic reads in a multi-node environment |
Dec. 26, 2006 |
| 7149863 |
System and method of descriptively specifying memory placement in a computer system |
Dec. 12, 2006 |
| 7149855 |
Network attached memory and implementation thereof |
Dec. 12, 2006 |
| 7149852 |
System and method for blocking data responses |
Dec. 12, 2006 |
| 7149851 |
Method and system for conservatively managing store capacity available to a processor issuing stores |
Dec. 12, 2006 |
| 7146484 |
Method and apparatus for caching storage system |
Dec. 5, 2006 |
| 7146469 |
Method, apparatus, and system for improving memory access speed |
Dec. 5, 2006 |
| 7146468 |
Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache |
Dec. 5, 2006 |
| 7143246 |
Method for supporting improved burst transfers on a coherent bus |
Nov. 28, 2006 |
| 7143244 |
System and method for invalidating data in a hierarchy of caches |
Nov. 28, 2006 |
| 7139880 |
Disk array device, method for controlling the disk array device and storage system |
Nov. 21, 2006 |
| 7136969 |
Using the message fabric to maintain cache coherency of local caches of global memory |
Nov. 14, 2006 |
| 7136968 |
System and method for maintaining cache consistency in a wireless communication system |
Nov. 14, 2006 |
| 7133976 |
Disk array device, method for controlling the disk array device and storage system |
Nov. 7, 2006 |
| 7133975 |
Cache memory system including a cache memory employing a tag including associated touch bits |
Nov. 7, 2006 |
| 7133974 |
Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
Nov. 7, 2006 |
| 7130969 |
Hierarchical directories for cache coherency in a multiprocessor system |
Oct. 31, 2006 |
| 7130964 |
Object caching and update queuing technique to improve performance and resource utilization |
Oct. 31, 2006 |
| 7130962 |
Writing cache lines on a disk drive |
Oct. 31, 2006 |
| 7130961 |
Disk controller and method of controlling the cache |
Oct. 31, 2006 |
| 7130953 |
Bus architecture techniques employing busses with different complexities |
Oct. 31, 2006 |
| 7127561 |
Coherency techniques for suspending execution of a thread until a specified memory access occurs |
Oct. 24, 2006 |
| 7127560 |
Method of dynamically controlling cache size |
Oct. 24, 2006 |
| 7124258 |
Storage system and storage device system |
Oct. 17, 2006 |
| 7124257 |
Bus interface controller for determining access counts |
Oct. 17, 2006 |
| 7124254 |
Method and structure for monitoring pollution and prefetches due to speculative accesses |
Oct. 17, 2006 |
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