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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7320054 |
Multiprocessor system having a shared memory |
Jan. 15, 2008 |
| 7320039 |
Method for processing consistent data sets |
Jan. 15, 2008 |
| 7318126 |
Asynchronous symmetric multiprocessing |
Jan. 8, 2008 |
| 7315919 |
Bandwidth reduction technique in a snooping-based cache-coherent cluster of multiprocessing nodes |
Jan. 1, 2008 |
| 7315912 |
Deadlock avoidance in a bus fabric |
Jan. 1, 2008 |
| 7310708 |
Cache system with groups of lines and with coherency for both single lines and groups of lines |
Dec. 18, 2007 |
| 7308539 |
Concurrent read access and exclusive write access to data in shared memory architecture |
Dec. 11, 2007 |
| 7308538 |
Scope-based cache coherence |
Dec. 11, 2007 |
| 7302529 |
Method for comparing contents of memory components |
Nov. 27, 2007 |
| 7296270 |
Method and control unit for controlling technical procedures in a motor vehicle |
Nov. 13, 2007 |
| 7296167 |
Combined system responses in a chip multiprocessor |
Nov. 13, 2007 |
| 7296122 |
Flexible probe/probe response routing for maintaining coherency |
Nov. 13, 2007 |
| 7296121 |
Reducing probe traffic in multiprocessor systems |
Nov. 13, 2007 |
| 7290085 |
Method and system for flexible and efficient protocol table implementation |
Oct. 30, 2007 |
| 7287125 |
Disk array device, method for controlling the disk array device and storage system |
Oct. 23, 2007 |
| 7284118 |
Method and apparatus for synchronizing load operations |
Oct. 16, 2007 |
| 7284031 |
Protocol-independent client-side caching system and method |
Oct. 16, 2007 |
| 7277992 |
Cache eviction technique for reducing cache eviction traffic |
Oct. 2, 2007 |
| 7272688 |
Methods and apparatus for providing cache state information |
Sep. 18, 2007 |
| 7269698 |
Hierarchical virtual model of a cache hierarchy in a multiprocessor system |
Sep. 11, 2007 |
| 7269695 |
Ambiguous virtual channels |
Sep. 11, 2007 |
| 7269694 |
Selectively monitoring loads to support transactional program execution |
Sep. 11, 2007 |
| 7269693 |
Selectively monitoring stores to support transactional program execution |
Sep. 11, 2007 |
| 7266647 |
List based method and apparatus for selective and rapid cache flushes |
Sep. 4, 2007 |
| 7266642 |
Cache residence prediction |
Sep. 4, 2007 |
| 7266587 |
System having interfaces, switch, and memory bridge for CC-NUMA operation |
Sep. 4, 2007 |
| 7263586 |
Cache coherency for multiple independent cache of a domain |
Aug. 28, 2007 |
| 7263585 |
Store-induced instruction coherency mechanism |
Aug. 28, 2007 |
| 7263580 |
Cache flush based on checkpoint timer |
Aug. 28, 2007 |
| 7257686 |
Memory controller and method for scrubbing memory without using explicit atomic operations |
Aug. 14, 2007 |
| 7257679 |
Sharing monitored cache lines across multiple cores |
Aug. 14, 2007 |
| 7254686 |
Switching between mirrored and non-mirrored volumes |
Aug. 7, 2007 |
| 7251694 |
Peer-to peer name resolution protocol (PNRP) security infrastructure and method |
Jul. 31, 2007 |
| 7249245 |
Globally observing load operations prior to fence instruction and post-serialization modes |
Jul. 24, 2007 |
| 7249224 |
Methods and apparatus for providing early responses from a remote data cache |
Jul. 24, 2007 |
| 7240174 |
System and method for migrating data between memories |
Jul. 3, 2007 |
| 7240157 |
System for handling memory requests and method thereof |
Jul. 3, 2007 |
| 7234029 |
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture |
Jun. 19, 2007 |
| 7234028 |
Power/performance optimized cache using memory write prevention through write snarfing |
Jun. 19, 2007 |
| 7231497 |
Merging write-back and write-through cache policies |
Jun. 12, 2007 |
| 7231492 |
Data transfer method wherein a sequence of messages update tag structures during a read data transfer |
Jun. 12, 2007 |
| 7228389 |
System and method for maintaining cache coherency in a shared memory system |
Jun. 5, 2007 |
| 7228386 |
Programmably disabling one or more cache entries |
Jun. 5, 2007 |
| 7225298 |
Multi-node computer system in which networks in different nodes implement different conveyance modes |
May. 29, 2007 |
| 7222221 |
Maintaining coherency of derived data in a computer system |
May. 22, 2007 |
| 7222220 |
Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices |
May. 22, 2007 |
| 7219199 |
System and method for increasing bandwidth in a directory based high speed memory system |
May. 15, 2007 |
| 7216204 |
Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
May. 8, 2007 |
| 7216202 |
Method and apparatus for supporting one or more servers on a single semiconductor chip |
May. 8, 2007 |
| 7213109 |
System and method for providing speculative ownership of cached data based on history tracking |
May. 1, 2007 |
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