| Patent Number |
Title Of Patent |
Date Issued |
| 6092159 |
Implementation of configurable on-chip fast memory using the data cache RAM |
Jul. 18, 2000 |
| 6088768 |
Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication |
Jul. 11, 2000 |
| 6088769 |
Multiprocessor cache coherence directed by combined local and global tables |
Jul. 11, 2000 |
| 6088770 |
Shared memory multiprocessor performing cache coherency |
Jul. 11, 2000 |
| 6085292 |
Apparatus and method for providing non-blocking pipelined cache |
Jul. 4, 2000 |
| 6085293 |
Non-uniform memory access (NUMA) data processing system that decreases latency by expediting rerun requests |
Jul. 4, 2000 |
| 6081874 |
Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect |
Jun. 27, 2000 |
| 6079002 |
Dynamic expansion of execution pipeline stages |
Jun. 20, 2000 |
| 6073211 |
Method and system for memory updates within a multiprocessor data processing system |
Jun. 6, 2000 |
| 6073216 |
System and method for reliable system shutdown after coherency corruption |
Jun. 6, 2000 |
| 6073217 |
Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor |
Jun. 6, 2000 |
| 6070231 |
Method and apparatus for processing memory requests that require coherency transactions |
May. 30, 2000 |
| 6070233 |
Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache |
May. 30, 2000 |
| 6067603 |
Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect |
May. 23, 2000 |
| 6065098 |
Method for maintaining multi-level cache coherency in a processor with non-inclusive caches and processor implementing the same |
May. 16, 2000 |
| 6061764 |
Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions |
May. 9, 2000 |
| 6061765 |
Independent victim data buffer and probe buffer release control utilzing control flag |
May. 9, 2000 |
| 6055610 |
Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations |
Apr. 25, 2000 |
| 6052760 |
Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks |
Apr. 18, 2000 |
| 6052761 |
Increment update in an SCI based system |
Apr. 18, 2000 |
| 6049809 |
Replication optimization system and method |
Apr. 11, 2000 |
| 6049851 |
Method and apparatus for checking cache coherency in a computer architecture |
Apr. 11, 2000 |
| 6049866 |
Method and system for an efficient user mode cache manipulation using a simulated instruction |
Apr. 11, 2000 |
| 6044438 |
Memory controller for controlling memory accesses across networks in distributed shared memory processing systems |
Mar. 28, 2000 |
| 6044478 |
Cache with finely granular locked-down regions |
Mar. 28, 2000 |
| 6038644 |
Multiprocessor system with partial broadcast capability of a cache coherent processing request |
Mar. 14, 2000 |
| 6038645 |
Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache |
Mar. 14, 2000 |
| 6032228 |
Flexible cache-coherency mechanism |
Feb. 29, 2000 |
| 6032230 |
Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory |
Feb. 29, 2000 |
| 6032231 |
Multiprocessor with split transaction bus architecture providing cache tag and address compare for sending retry direction to other bus module upon a match of subsequent address bus cycles to |
Feb. 29, 2000 |
| 6029204 |
Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries |
Feb. 22, 2000 |
| 6023747 |
Method and system for handling conflicts between cache operation requests in a data processing system |
Feb. 8, 2000 |
| 6021472 |
Information processing device and control method thereof |
Feb. 1, 2000 |
| 6021473 |
Method and apparatus for maintaining coherency for data transaction of CPU and bus device utilizing selective flushing mechanism |
Feb. 1, 2000 |
| 6021474 |
Apparatus and method of snooping processors and look-aside caches |
Feb. 1, 2000 |
| 6018763 |
High performance shared memory for a bridge router supporting cache coherency |
Jan. 25, 2000 |
| 6018791 |
Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states |
Jan. 25, 2000 |
| 6016532 |
Method for handling data cache misses using help instructions |
Jan. 18, 2000 |
| 6014751 |
Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state |
Jan. 11, 2000 |
| 6012127 |
Multiprocessor computing apparatus with optional coherency directory |
Jan. 4, 2000 |
| 6012134 |
High-performance processor with streaming buffer that facilitates prefetching of instructions |
Jan. 4, 2000 |
| 6003116 |
Multiplexed computer system with the capability to copy data from one processor memory to another |
Dec. 14, 1999 |
| 6000015 |
Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache |
Dec. 7, 1999 |
| 5996049 |
Cache-coherency protocol with recently read state for data and instructions |
Nov. 30, 1999 |
| 5996050 |
Cache coherency detection in a bus bridge verification system |
Nov. 30, 1999 |
| 5987496 |
Real-time channel-based reflective memory |
Nov. 16, 1999 |
| 5987571 |
Cache coherency control method and multi-processor system using the same |
Nov. 16, 1999 |
| 5978886 |
Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache |
Nov. 2, 1999 |
| 5974509 |
Method for purging unused data from a cache memory |
Oct. 26, 1999 |
| 5974511 |
Cache subsystem with pseudo-packet switch |
Oct. 26, 1999 |
