| Patent Number |
Title Of Patent |
Date Issued |
| 6205507 |
Memory coherency in a processor-to-bus cycle in a multi-processor system |
Mar. 20, 2001 |
| 6205517 |
Main memory control apparatus for use in a memory having non-cacheable address space allocated to DMA accesses |
Mar. 20, 2001 |
| 6202131 |
Method and apparatus for executing variable delay system bus operations of differing type or character without dead lock using shared buffers |
Mar. 13, 2001 |
| 6202132 |
Flexible cache-coherency mechanism |
Mar. 13, 2001 |
| 6199143 |
Computing system with fast data transfer of CPU state related information |
Mar. 6, 2001 |
| 6199147 |
Distributed-memory multiprocessor computer system with directory-based cache coherency with ambiguous mappings of cached data to main-memory locations |
Mar. 6, 2001 |
| 6195728 |
Detection of hot points in a non-uniform memory access machine |
Feb. 27, 2001 |
| 6195731 |
Instrumentation device for a machine with non-uniform memory access |
Feb. 27, 2001 |
| 6192451 |
Cache coherency protocol for a data processing system including a multi-level memory hierarchy |
Feb. 20, 2001 |
| 6192452 |
Method and system for avoiding data loss due to cancelled transactions within a non-uniform memory access system |
Feb. 20, 2001 |
| 6189075 |
Circuit for the management of memories in a multiple-user environment with access request and priority |
Feb. 13, 2001 |
| 6182195 |
System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer |
Jan. 30, 2001 |
| 6182196 |
Method and apparatus for arbitrating access requests to a memory |
Jan. 30, 2001 |
| 6182201 |
Demand-based issuance of cache operations to a system bus |
Jan. 30, 2001 |
| 6178484 |
DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches |
Jan. 23, 2001 |
| 6173370 |
Cache system capable of keeping cache-coherency among store-in-caches of two central processing units on occurrence of store-confliction |
Jan. 9, 2001 |
| 6164840 |
Ensuring consistency of an instruction cache with a store cache check and an execution blocking flush instruction in an instruction queue |
Dec. 26, 2000 |
| 6167489 |
System and method for bypassing supervisory memory intervention for data transfers between devices having local memories |
Dec. 26, 2000 |
| 6163801 |
Dynamic communication between computer processes |
Dec. 19, 2000 |
| 6157977 |
Bus bridge and method for ordering read and write operations in a write posting system |
Dec. 5, 2000 |
| 6154816 |
Low occupancy protocol for managing concurrent transactions with dependencies |
Nov. 28, 2000 |
| 6151670 |
Method for conserving memory storage using a pool of short term memory registers |
Nov. 21, 2000 |
| 6148378 |
Process for operating a machine with non-uniform memory access and cache coherency and a machine for implementing the process |
Nov. 14, 2000 |
| 6145059 |
Cache coherency protocols with posted operations and tagged coherency states |
Nov. 7, 2000 |
| 6141733 |
Cache coherency protocol with independent implementation of optimized cache operations |
Oct. 31, 2000 |
| 6138124 |
Field level replication method |
Oct. 24, 2000 |
| 6138217 |
Method and apparatus for cache coherency in an interconnecting network |
Oct. 24, 2000 |
| 6138218 |
Forward progress on retried snoop hits by altering the coherency state of a local cache |
Oct. 24, 2000 |
| 6138226 |
Logical cache memory storing logical and physical address information for resolving synonym problems |
Oct. 24, 2000 |
| 6134634 |
Method and apparatus for preemptive cache write-back |
Oct. 17, 2000 |
| 6128705 |
Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations |
Oct. 3, 2000 |
| 6128706 |
Apparatus and method for a load bias--load with intent to semaphore |
Oct. 3, 2000 |
| 6128711 |
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes |
Oct. 3, 2000 |
| 6122711 |
Method of and apparatus for store-in second level cache flush |
Sep. 19, 2000 |
| 6122712 |
Cache coherency controller of cache memory for maintaining data anti-dependence when threads are executed in parallel |
Sep. 19, 2000 |
| 6122714 |
Order supporting mechanisms for use in a switch-based multi-processor system |
Sep. 19, 2000 |
| 6119150 |
Message passing distributed shared memory system that eliminates unnecessary software controlled cache flushes or purges |
Sep. 12, 2000 |
| 6119197 |
Method for providing and operating upgradeable cache circuitry |
Sep. 12, 2000 |
| 6119204 |
Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization |
Sep. 12, 2000 |
| 6115794 |
Method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system |
Sep. 5, 2000 |
| 6115795 |
Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system |
Sep. 5, 2000 |
| 6115804 |
Non-uniform memory access (NUMA) data processing system that permits multiple caches to concurrently hold data in a recent state from which data can be sourced by shared intervention |
Sep. 5, 2000 |
| 6112281 |
I/O forwarding in a cache coherent shared disk computer system |
Aug. 29, 2000 |
| 6108721 |
Method and apparatus for ensuring data consistency between an i/o channel and a processor |
Aug. 22, 2000 |
| 6108764 |
Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention |
Aug. 22, 2000 |
| 6105112 |
Dynamic folding of cache operations for multiple coherency-size systems |
Aug. 15, 2000 |
| 6101581 |
Separate victim buffer read and release control |
Aug. 8, 2000 |
| 6101582 |
Dcbst with icbi mechanism |
Aug. 8, 2000 |
| 6094709 |
Cache coherence for lazy entry consistency in lockup-free caches |
Jul. 25, 2000 |
| 6092156 |
System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations |
Jul. 18, 2000 |
