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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6298420 |
Coherent variable length reads from system memory |
Oct. 2, 2001 |
| 6295477 |
Bus coupler between a system bus and a local bus in a multiple processor data processing system |
Sep. 25, 2001 |
| 6295585 |
High-performance communication method and apparatus for write-only networks |
Sep. 25, 2001 |
| 6295600 |
Thread switch on blocked load or store using instruction thread field |
Sep. 25, 2001 |
| 6292872 |
Cache coherency protocol having hovering (H) and recent (R) states |
Sep. 18, 2001 |
| 6292879 |
Method and apparatus to specify access control list and cache enabling and cache coherency requirement enabling on individual operands of an instruction of a computer |
Sep. 18, 2001 |
| 6289419 |
Consistency control device merging updated memory blocks |
Sep. 11, 2001 |
| 6289420 |
System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem |
Sep. 11, 2001 |
| 6289438 |
Microprocessor cache redundancy scheme using store buffer |
Sep. 11, 2001 |
| 6286081 |
Mechanism for ensuring data coherency during sequential readings of portions of data that changes with time |
Sep. 4, 2001 |
| 6279084 |
Shadow commands to optimize sequencing of requests in a switch-based multi-processor system |
Aug. 21, 2001 |
| 6279085 |
Method and system for avoiding livelocks due to colliding writebacks within a non-uniform memory access system |
Aug. 21, 2001 |
| 6275900 |
Hybrid NUMA/S-COMA system and method |
Aug. 14, 2001 |
| 6275905 |
Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system |
Aug. 14, 2001 |
| 6275906 |
Coherency maintenance in a multiprocessor system |
Aug. 14, 2001 |
| 6272599 |
Cache structure and method for improving worst case execution time |
Aug. 7, 2001 |
| 6272649 |
Method and system for ensuring cache file integrity |
Aug. 7, 2001 |
| 6269428 |
Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system |
Jul. 31, 2001 |
| 6269432 |
Distributed transactional processing system having redundant data |
Jul. 31, 2001 |
| 6266743 |
Method and system for providing an eviction protocol within a non-uniform memory access system |
Jul. 24, 2001 |
| 6263347 |
System for linking data between computer and portable remote terminal and data linking method therefor |
Jul. 17, 2001 |
| 6263403 |
Method and apparatus for linking translation lookaside buffer purge operations to cache coherency transactions |
Jul. 17, 2001 |
| 6263405 |
Multiprocessor system |
Jul. 17, 2001 |
| 6263406 |
Parallel processor synchronization and coherency control method and system |
Jul. 17, 2001 |
| 6263407 |
Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode |
Jul. 17, 2001 |
| 6260117 |
Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency |
Jul. 10, 2001 |
| 6260118 |
Snooping a variable number of cache addresses in a multiple processor system by a single snoop request |
Jul. 10, 2001 |
| 6260119 |
Memory cache management for isochronous memory access |
Jul. 10, 2001 |
| 6256710 |
Cache management during cache inhibited transactions for increasing cache efficiency |
Jul. 3, 2001 |
| 6256712 |
Scaleable method for maintaining and making consistent updates to caches |
Jul. 3, 2001 |
| 6256713 |
Bus optimization with read/write coherence including ordering responsive to collisions |
Jul. 3, 2001 |
| 6253290 |
Multiprocessor system capable of circumventing write monitoring of cache memories |
Jun. 26, 2001 |
| 6249845 |
Method for supporting cache control instructions within a coherency granule |
Jun. 19, 2001 |
| 6249851 |
Computer system having non-blocking cache and pipelined bus interface unit |
Jun. 19, 2001 |
| 6247098 |
Cache coherency protocol with selectively implemented tagged state |
Jun. 12, 2001 |
| 6247099 |
System and method for maintaining cache coherency and data synchronization in a computer system having multiple active controllers |
Jun. 12, 2001 |
| 6247100 |
Method and system for transmitting address commands in a multiprocessor system |
Jun. 12, 2001 |
| 6243794 |
Data-processing system with CC-NUMA (cache-coherent, non-uniform memory access) architecture and remote cache incorporated in local memory |
Jun. 5, 2001 |
| 6240490 |
Comprehensive multilevel cache preloading mechanism in a multiprocessing simulation environment |
May. 29, 2001 |
| 6237083 |
Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an ins |
May. 22, 2001 |
| 6233627 |
Processor with internal register for peripheral status |
May. 15, 2001 |
| 6226694 |
Achieving consistency and synchronization among multiple data stores that cooperate within a single system in the absence of transaction monitoring |
May. 1, 2001 |
| 6223259 |
Reducing read cycle of memory read request for data to be partially modified by a pending write request |
Apr. 24, 2001 |
| 6223260 |
Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states |
Apr. 24, 2001 |
| 6219755 |
Upgradeable cache circuit using high speed multiplexer |
Apr. 17, 2001 |
| 6219761 |
Load/store assist engine |
Apr. 17, 2001 |
| 6209063 |
Management of the information flow within a computer system |
Mar. 27, 2001 |
| 6209064 |
Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system |
Mar. 27, 2001 |
| 6209065 |
Mechanism for optimizing generation of commit-signals in a distributed shared-memory system |
Mar. 27, 2001 |
| 6209068 |
Read line buffer and signaling protocol for processor |
Mar. 27, 2001 |
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