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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6393526 |
Shared cache parsing and pre-fetch |
May. 21, 2002 |
| 6393528 |
Optimized cache allocation algorithm for multiple speculative requests |
May. 21, 2002 |
| 6393529 |
Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write |
May. 21, 2002 |
| 6389515 |
System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations |
May. 14, 2002 |
| 6389526 |
Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system |
May. 14, 2002 |
| 6389527 |
Microprocessor allowing simultaneous instruction execution and DMA transfer |
May. 14, 2002 |
| 6385676 |
Coherent ordering queue for computer system |
May. 7, 2002 |
| 6385701 |
Method, system and program products for sharing data between varied clients using token management |
May. 7, 2002 |
| 6385702 |
High performance multiprocessor system with exclusive-deallocate cache state |
May. 7, 2002 |
| 6378044 |
Method and system for cache replacement among configurable cache sets |
Apr. 23, 2002 |
| 6374329 |
High-availability super server |
Apr. 16, 2002 |
| 6374330 |
Cache-coherency protocol with upstream undefined state |
Apr. 16, 2002 |
| 6374331 |
Distributed directory cache coherence multi-processor computer architecture |
Apr. 16, 2002 |
| 6370621 |
Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation |
Apr. 9, 2002 |
| 6366984 |
Write combining buffer that supports snoop request |
Apr. 2, 2002 |
| 6367005 |
System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch |
Apr. 2, 2002 |
| 6363458 |
Adaptive granularity method for integration of fine and coarse communication in the distributed shared memory system |
Mar. 26, 2002 |
| 6360298 |
Load/store instruction control circuit of microprocessor and load/store instruction control method |
Mar. 19, 2002 |
| 6360301 |
Coherency protocol for computer cache |
Mar. 19, 2002 |
| 6356981 |
Method and apparatus for preserving data coherency in a double data rate SRAM |
Mar. 12, 2002 |
| 6356991 |
Programmable address translation system |
Mar. 12, 2002 |
| 6353877 |
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write |
Mar. 5, 2002 |
| 6351790 |
Cache coherency mechanism |
Feb. 26, 2002 |
| 6351791 |
Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responses |
Feb. 26, 2002 |
| 6349366 |
Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands |
Feb. 19, 2002 |
| 6347361 |
Cache coherency protocols with posted operations |
Feb. 12, 2002 |
| 6345320 |
DMA address buffer and cache-memory control system |
Feb. 5, 2002 |
| 6345339 |
Pseudo precise I-cache inclusivity for vertical caches |
Feb. 5, 2002 |
| 6345340 |
Cache coherency protocol with ambiguous state for posted operations |
Feb. 5, 2002 |
| 6345341 |
Method of cache management for dynamically disabling O state memory-consistent data |
Feb. 5, 2002 |
| 6341336 |
Cache coherency protocol having tagged state used with cross-bars |
Jan. 22, 2002 |
| 6339812 |
Method and apparatus for handling invalidation requests to processors not present in a computer system |
Jan. 15, 2002 |
| 6338098 |
Processor with internal register for peripheral status |
Jan. 8, 2002 |
| 6338119 |
Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance |
Jan. 8, 2002 |
| 6338122 |
Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node |
Jan. 8, 2002 |
| 6336168 |
System and method for merging multiple outstanding load miss instructions |
Jan. 1, 2002 |
| 6334172 |
Cache coherency protocol with tagged state for modified values |
Dec. 25, 2001 |
| 6332178 |
Method for estimating statistics of properties of memory system transactions |
Dec. 18, 2001 |
| 6330643 |
Cache coherency protocols with global and local posted operations |
Dec. 11, 2001 |
| 6324622 |
6XX bus with exclusive intervention |
Nov. 27, 2001 |
| 6321297 |
Avoiding tag compares during writes in multi-level cache hierarchy |
Nov. 20, 2001 |
| 6321298 |
Full cache coherency across multiple raid controllers |
Nov. 20, 2001 |
| 6321304 |
System and method for deleting read-only head entries in multi-processor computer systems supporting cache coherence with mixed protocols |
Nov. 20, 2001 |
| 6321306 |
High performance multiprocessor system with modified-unsolicited cache state |
Nov. 20, 2001 |
| 6314495 |
Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations |
Nov. 6, 2001 |
| 6314496 |
Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands |
Nov. 6, 2001 |
| 6314497 |
Apparatus and method for maintaining cache coherency in a memory system |
Nov. 6, 2001 |
| 6311280 |
Low-power memory system with incorporated vector processing |
Oct. 30, 2001 |
| 6304945 |
Method and apparatus for maintaining cache coherency in a computer system having multiple processor buses |
Oct. 16, 2001 |
| 6298415 |
Method and system for minimizing writes and reducing parity updates in a raid system |
Oct. 2, 2001 |
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