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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6490655 |
Data processing apparatus and method for cache line replacement responsive to the operational state of memory |
Dec. 3, 2002 |
| 6490659 |
Warm start cache recovery in a dual active controller with cache coherency using stripe locks for implied storage volume reservations |
Dec. 3, 2002 |
| 6490660 |
Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system |
Dec. 3, 2002 |
| 6490661 |
Maintaining cache coherency during a memory read operation in a multiprocessing computer system |
Dec. 3, 2002 |
| 6487638 |
System and method for time weighted access frequency based caching for memory controllers |
Nov. 26, 2002 |
| 6487641 |
Dynamic caches with miss tables |
Nov. 26, 2002 |
| 6484237 |
Unified multilevel memory system architecture which supports both cache and addressable SRAM |
Nov. 19, 2002 |
| 6484240 |
Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols |
Nov. 19, 2002 |
| 6484241 |
Multiprocessor computer system with sectored cache line system bus protocol mechanism |
Nov. 19, 2002 |
| 6481251 |
Store queue number assignment and tracking |
Nov. 19, 2002 |
| 6480937 |
Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)-- |
Nov. 12, 2002 |
| 6480940 |
Method of controlling cache memory in multiprocessor system and the multiprocessor system based on detection of predetermined software module |
Nov. 12, 2002 |
| 6477622 |
Simplified writeback handling |
Nov. 5, 2002 |
| 6470429 |
System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops |
Oct. 22, 2002 |
| 6466988 |
Multiprocessor synchronization and coherency control system |
Oct. 15, 2002 |
| 6467012 |
Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors |
Oct. 15, 2002 |
| 6467027 |
Method and system for an INUSE field resource management scheme |
Oct. 15, 2002 |
| 6463501 |
Method, system and program for maintaining data consistency among updates across groups of storage areas using update times |
Oct. 8, 2002 |
| 6463507 |
Layered local cache with lower level cache updating upper and lower level cache directories |
Oct. 8, 2002 |
| 6463509 |
Preloading data in a cache memory according to user-specified preload criteria |
Oct. 8, 2002 |
| 6463510 |
Apparatus for identifying memory requests originating on remote I/O devices as noncacheable |
Oct. 8, 2002 |
| 6460119 |
Snoop blocking for cache coherency |
Oct. 1, 2002 |
| 6457104 |
System and method for recycling stale memory content in compressed memory systems |
Sep. 24, 2002 |
| 6453391 |
Multiplexed computer system |
Sep. 17, 2002 |
| 6453408 |
System and method for memory page migration in a multi-processor computer |
Sep. 17, 2002 |
| 6449614 |
Interface system and method for asynchronously updating a share resource with locking facility |
Sep. 10, 2002 |
| 6446166 |
Method for upper level cache victim selection management by a lower level cache |
Sep. 3, 2002 |
| 6446241 |
Automated method for testing cache |
Sep. 3, 2002 |
| 6442597 |
Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory |
Aug. 27, 2002 |
| 6442651 |
Shared cache parsing and pre-fetch |
Aug. 27, 2002 |
| 6442653 |
Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data |
Aug. 27, 2002 |
| 6442654 |
Operating system support for in-server caching of documents |
Aug. 27, 2002 |
| 6438654 |
Castout processing for duplexed cache structures |
Aug. 20, 2002 |
| 6438658 |
Fast invalidation scheme for caches |
Aug. 20, 2002 |
| 6438659 |
Directory based cache coherency system supporting multiple instruction processor and input/output caches |
Aug. 20, 2002 |
| 6434665 |
Cache memory store buffer |
Aug. 13, 2002 |
| 6430659 |
Method and means for increasing performance of multiprocessor computer systems by reducing accesses to global memory locations through the use of quanta |
Aug. 6, 2002 |
| 6427189 |
Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline |
Jul. 30, 2002 |
| 6418513 |
Queue-less and state-less layered local data cache mechanism |
Jul. 9, 2002 |
| 6418514 |
Removal of posted operations from cache operations queue |
Jul. 9, 2002 |
| 6415361 |
Apparatus for controlling cache by using dual-port transaction buffers |
Jul. 2, 2002 |
| 6415364 |
High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems |
Jul. 2, 2002 |
| 6412047 |
Coherency protocol |
Jun. 25, 2002 |
| 6408362 |
Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data |
Jun. 18, 2002 |
| 6408363 |
Speculative pre-flush of data in an out-of-order execution processor system |
Jun. 18, 2002 |
| 6405289 |
Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response |
Jun. 11, 2002 |
| 6401172 |
Recycle mechanism for a processing agent |
Jun. 4, 2002 |
| 6401173 |
Method and apparatus for optimizing bcache tag performance by inferring bcache tag state from internal processor state |
Jun. 4, 2002 |
| 6401176 |
Multiple agent use of a multi-ported shared memory |
Jun. 4, 2002 |
| 6397302 |
Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system |
May. 28, 2002 |
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