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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6591336 |
Technique for maintaining coherency between shared-disk and disk caches |
Jul. 8, 2003 |
| 6591348 |
Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system |
Jul. 8, 2003 |
| 6587865 |
Locally made, globally coordinated resource allocation decisions based on information provided by the second-price auction model |
Jul. 1, 2003 |
| 6587921 |
Method and apparatus for cache synchronization in a clustered environment |
Jul. 1, 2003 |
| 6587924 |
Scarfing within a hierarchical memory architecture |
Jul. 1, 2003 |
| 6587926 |
Incremental tag build for hierarchical memory architecture |
Jul. 1, 2003 |
| 6587929 |
Apparatus and method for performing write-combining in a pipelined microprocessor using tags |
Jul. 1, 2003 |
| 6581112 |
Direct memory access (DMA) receiver |
Jun. 17, 2003 |
| 6578065 |
Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory |
Jun. 10, 2003 |
| 6578113 |
Method for cache validation for proxy caches |
Jun. 10, 2003 |
| 6578114 |
Method and apparatus for altering data length to zero to maintain cache coherency |
Jun. 10, 2003 |
| 6578115 |
Method and apparatus for handling invalidation requests to processors not present in a computer system |
Jun. 10, 2003 |
| 6578116 |
Snoop blocking for cache coherency |
Jun. 10, 2003 |
| 6574710 |
Computer cache system with deferred invalidation |
Jun. 3, 2003 |
| 6574714 |
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache |
Jun. 3, 2003 |
| 6574715 |
Method and apparatus for managing internal caches and external caches in a data processing system |
Jun. 3, 2003 |
| 6571278 |
Computer data sharing system and method for maintaining replica consistency |
May. 27, 2003 |
| 6571320 |
Cache memory for two-dimensional data fields |
May. 27, 2003 |
| 6571321 |
Read exclusive for fast, simple invalidate |
May. 27, 2003 |
| 6571322 |
Multiprocessor computer system with sectored cache line mechanism for cache intervention |
May. 27, 2003 |
| 6571329 |
Detection of overwrite modification by preceding instruction possibility of fetched instruction code using fetched instructions counter and store target address |
May. 27, 2003 |
| 6567885 |
System and method for address broadcast synchronization using a plurality of switches |
May. 20, 2003 |
| 6567896 |
System and method for deleting read-only head entries in multi-processor computer systems supporting cache coherence with mixed protocols |
May. 20, 2003 |
| 6564272 |
Non-coherent cache buffer for read accesses to system memory |
May. 13, 2003 |
| 6564298 |
Front end system having multiple decoding modes |
May. 13, 2003 |
| 6564302 |
Information processing apparatus with cache coherency |
May. 13, 2003 |
| 6564306 |
Apparatus and method for performing speculative cache directory tag updates |
May. 13, 2003 |
| 6560674 |
Data cache system |
May. 6, 2003 |
| 6557048 |
Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof |
Apr. 29, 2003 |
| 6557076 |
Method and apparatus for aggressively rendering data in a data processing system |
Apr. 29, 2003 |
| 6557082 |
Method and apparatus for ensuring cache coherency for spawned dependent transactions in a multi-system environment with shared data storage devices |
Apr. 29, 2003 |
| 6553430 |
Computer system implementing flush operation |
Apr. 22, 2003 |
| 6553462 |
Multiprocessor computer system with sectored cache line mechanism for load and store operations |
Apr. 22, 2003 |
| 6549988 |
Data storage system comprising a network of PCs and method using same |
Apr. 15, 2003 |
| 6546464 |
Method and apparatus for increasing data rates in a data network while maintaining system coherency |
Apr. 8, 2003 |
| 6546467 |
Cache coherency mechanism using an operation to be executed on the contents of a location in a cache specifying an address in main memory |
Apr. 8, 2003 |
| 6546471 |
Shared memory multiprocessor performing cache coherency |
Apr. 8, 2003 |
| 6529968 |
DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces |
Mar. 4, 2003 |
| 6529999 |
Computer system implementing system and method for ordering write operations and maintaining memory coherency |
Mar. 4, 2003 |
| 6526480 |
Cache apparatus and control method allowing speculative processing of data |
Feb. 25, 2003 |
| 6526481 |
Adaptive cache coherence protocols |
Feb. 25, 2003 |
| 6519685 |
Cache states for multiprocessor cache coherency protocols |
Feb. 11, 2003 |
| 6515759 |
Printer having processor with instruction cache and compressed program store |
Feb. 4, 2003 |
| 6502168 |
Cache having virtual cache controller queues |
Dec. 31, 2002 |
| 6502170 |
Memory-to-memory compare/exchange instructions to support non-blocking synchronization schemes |
Dec. 31, 2002 |
| 6496904 |
Method and apparatus for efficient tracking of bus coherency by using a single coherency tag bank |
Dec. 17, 2002 |
| 6496907 |
System and method for updating from a read-only to a read-write entry and concurrently invalidating stale cache copies from head-to-tail and tail-to-head directions |
Dec. 17, 2002 |
| 6493798 |
Upgradeable cache circuit using high speed multiplexer |
Dec. 10, 2002 |
| 6493802 |
Method and apparatus for performing speculative memory fills into a microprocessor |
Dec. 10, 2002 |
| 6490654 |
Method and apparatus for replacing cache lines in a cache memory |
Dec. 3, 2002 |
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