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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6647465 |
Realtime parallel processor system for transferring common information among parallel processors to a cache memory system |
Nov. 11, 2003 |
| 6647469 |
Using read current transactions for improved performance in directory-based coherent I/O systems |
Nov. 11, 2003 |
| 6643741 |
Method and apparatus for efficient cache management and avoiding unnecessary cache traffic |
Nov. 4, 2003 |
| 6640285 |
Method and apparatus for improving the efficiency of cache memories using stored activity measures |
Oct. 28, 2003 |
| 6640287 |
Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests |
Oct. 28, 2003 |
| 6640288 |
Read exclusive for fast, simple invalidate |
Oct. 28, 2003 |
| 6640289 |
Software controlled cache line ownership affinity enhancements in a multiprocessor environment |
Oct. 28, 2003 |
| 6636906 |
Apparatus and method for ensuring forward progress in coherent I/O systems |
Oct. 21, 2003 |
| 6636926 |
Shared memory multiprocessor performing cache coherence control and node controller therefor |
Oct. 21, 2003 |
| 6636939 |
Method and apparatus for processor bypass path to system memory |
Oct. 21, 2003 |
| 6636946 |
System and method for caching data based on identity of requestor |
Oct. 21, 2003 |
| 6636947 |
Coherency for DMA read cached data |
Oct. 21, 2003 |
| 6636948 |
Method and system for a processor to gain assured ownership of an up-to-date copy of data |
Oct. 21, 2003 |
| 6636949 |
System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing |
Oct. 21, 2003 |
| 6636950 |
Computer architecture for shared memory access |
Oct. 21, 2003 |
| 6633958 |
Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure |
Oct. 14, 2003 |
| 6633959 |
Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data |
Oct. 14, 2003 |
| 6631447 |
Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed |
Oct. 7, 2003 |
| 6631448 |
Cache coherence unit for interconnecting multiprocessor nodes having pipelined snoopy protocol |
Oct. 7, 2003 |
| 6631449 |
Dynamic distributed data system and method |
Oct. 7, 2003 |
| 6631450 |
Symmetric multiprocessor address bus protocol with intra-cache line access information |
Oct. 7, 2003 |
| 6631489 |
Cache memory and system with partial error detection and correction of MESI protocol |
Oct. 7, 2003 |
| 6629205 |
System and method for increasing the snoop bandwidth to cache tags in a cache memory subsystem |
Sep. 30, 2003 |
| 6629209 |
Cache coherency protocol permitting sharing of a locked data granule |
Sep. 30, 2003 |
| 6629210 |
Intelligent cache management mechanism via processor access sequence analysis |
Sep. 30, 2003 |
| 6629211 |
Method and system for improving raid controller performance through adaptive write back/write through caching |
Sep. 30, 2003 |
| 6629212 |
High speed lock acquisition mechanism with time parameterized cache coherency states |
Sep. 30, 2003 |
| 6629214 |
Extended cache coherency protocol with a persistent "lock acquired" state |
Sep. 30, 2003 |
| 6625698 |
Method and apparatus for controlling memory storage locks based on cache line ownership |
Sep. 23, 2003 |
| 6625701 |
Extended cache coherency protocol with a modified store instruction lock release indicator |
Sep. 23, 2003 |
| 6622214 |
System and method for maintaining memory coherency in a computer system having multiple system buses |
Sep. 16, 2003 |
| 6622215 |
Mechanism for handling conflicts in a multi-node computer architecture |
Sep. 16, 2003 |
| 6622216 |
Bus snooping for cache coherency for a bus without built-in bus snooping capabilities |
Sep. 16, 2003 |
| 6622217 |
Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system |
Sep. 16, 2003 |
| 6622218 |
Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system |
Sep. 16, 2003 |
| 6615319 |
Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture |
Sep. 2, 2003 |
| 6615320 |
Store collapsing mechanism for SMP computer system |
Sep. 2, 2003 |
| 6615321 |
Mechanism for collapsing store misses in an SMP computer system |
Sep. 2, 2003 |
| 6615322 |
Two-stage request protocol for accessing remote memory data in a NUMA data processing system |
Sep. 2, 2003 |
| 6611906 |
Self-organizing hardware processing entities that cooperate to execute requests |
Aug. 26, 2003 |
| 6604185 |
Distribution of address-translation-purge requests to multiple processors |
Aug. 5, 2003 |
| 6601145 |
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls |
Jul. 29, 2003 |
| 6601147 |
Computer system and method for maintaining an integrated shared buffer memory in a group of interconnected hosts |
Jul. 29, 2003 |
| 6598119 |
Database management system with a multiple-level cache arrangement |
Jul. 22, 2003 |
| 6598123 |
Snoop filter line replacement for reduction of back invalidates in multi-node architectures |
Jul. 22, 2003 |
| 6598140 |
Memory controller having separate agents that process memory transactions in parallel |
Jul. 22, 2003 |
| 6594733 |
Cache based vector coherency methods and mechanisms for tracking and managing data use in a multiprocessor system |
Jul. 15, 2003 |
| 6594741 |
Versatile write buffer for a microprocessor and method using same |
Jul. 15, 2003 |
| 6591307 |
Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response |
Jul. 8, 2003 |
| 6591321 |
Multiprocessor system bus protocol with group addresses, responses, and priorities |
Jul. 8, 2003 |
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