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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6721856 |
Enhanced cache management mechanism via an intelligent system bus monitor |
Apr. 13, 2004 |
| 6718442 |
Method and system for using high count invalidate acknowledgements in distributed shared memory systems |
Apr. 6, 2004 |
| 6718446 |
Storage media with benchmark representative of data originally stored thereon |
Apr. 6, 2004 |
| 6714994 |
Host bridge translating non-coherent packets from non-coherent link to coherent packets on conherent link and vice versa |
Mar. 30, 2004 |
| 6715040 |
Performance improvement of a write instruction of a non-inclusive hierarchical cache memory unit |
Mar. 30, 2004 |
| 6711650 |
Method and apparatus for accelerating input/output processing using cache injections |
Mar. 23, 2004 |
| 6711651 |
Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching |
Mar. 23, 2004 |
| 6711652 |
Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data |
Mar. 23, 2004 |
| 6708256 |
Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes |
Mar. 16, 2004 |
| 6708269 |
Method and apparatus for multi-mode fencing in a microprocessor system |
Mar. 16, 2004 |
| 6704833 |
Atomic transfer of a block of data |
Mar. 9, 2004 |
| 6704841 |
Method and apparatus for facilitating speculative stores in a multiprocessor system |
Mar. 9, 2004 |
| 6704842 |
Multi-processor system with proactive speculative data transfer |
Mar. 9, 2004 |
| 6704844 |
Dynamic hardware and software performance optimizations for super-coherent SMP systems |
Mar. 9, 2004 |
| 6701416 |
Cache coherency protocol with tagged intervention of modified values |
Mar. 2, 2004 |
| 6701417 |
Method and apparatus for supporting multiple cache line invalidations per cycle |
Mar. 2, 2004 |
| 6697849 |
System and method for caching JavaServer Pages.TM. responses |
Feb. 24, 2004 |
| 6697919 |
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system |
Feb. 24, 2004 |
| 6697925 |
Use of a cache ownership mechanism to synchronize multiple dayclocks |
Feb. 24, 2004 |
| 6694409 |
Cache states for multiprocessor cache coherency protocols |
Feb. 17, 2004 |
| 6687698 |
Accessing and updating a configuration database from distributed physical locations within a process control system |
Feb. 3, 2004 |
| 6687788 |
Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.) |
Feb. 3, 2004 |
| 6684305 |
Multiprocessor system implementing virtual memory using a shared memory, and a page replacement method for maintaining paged memory coherence |
Jan. 27, 2004 |
| 6681283 |
Coherent data apparatus for an on-chip split transaction system bus |
Jan. 20, 2004 |
| 6681292 |
Distributed read and write caching implementation for optimized input/output applications |
Jan. 20, 2004 |
| 6681320 |
Causality-based memory ordering in a multiprocessing environment |
Jan. 20, 2004 |
| 6678798 |
System and method for reducing memory latency during read requests |
Jan. 13, 2004 |
| 6678799 |
Aggregation of cache-updates in a multi-processor, shared-memory system |
Jan. 13, 2004 |
| 6678800 |
Cache apparatus and control method having writable modified state |
Jan. 13, 2004 |
| 6678809 |
Write-ahead log in directory management for concurrent I/O access for block storage |
Jan. 13, 2004 |
| 6675262 |
Multi-processor computer system with cache-flushing system using memory recall |
Jan. 6, 2004 |
| 6675264 |
Method and apparatus for improving write performance in a cluster-based file system |
Jan. 6, 2004 |
| 6675265 |
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants |
Jan. 6, 2004 |
| 6671782 |
Method and apparatus for processing read requests in a shared disk system |
Dec. 30, 2003 |
| 6668308 |
Scalable architecture based on single-chip multiprocessing |
Dec. 23, 2003 |
| 6668309 |
Snoop blocking for cache coherency |
Dec. 23, 2003 |
| 6665783 |
Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes |
Dec. 16, 2003 |
| 6662275 |
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache |
Dec. 9, 2003 |
| 6662277 |
Cache system with groups of lines and with coherency for both single lines and groups of lines |
Dec. 9, 2003 |
| 6658536 |
Cache-coherency protocol with recently read state for extending cache horizontally |
Dec. 2, 2003 |
| 6658537 |
DMA driven processor cache |
Dec. 2, 2003 |
| 6658538 |
Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control |
Dec. 2, 2003 |
| 6658539 |
Super-coherent data mechanisms for shared caches in a multiprocessing system |
Dec. 2, 2003 |
| 6654857 |
Non-uniform memory access (NUMA) computer system having distributed global coherency management |
Nov. 25, 2003 |
| 6651088 |
Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs |
Nov. 18, 2003 |
| 6651115 |
DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces |
Nov. 18, 2003 |
| 6651145 |
Method and apparatus for scalable disambiguated coherence in shared storage hierarchies |
Nov. 18, 2003 |
| 6651157 |
Multi-processor system and method of accessing data therein |
Nov. 18, 2003 |
| 6647453 |
System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system |
Nov. 11, 2003 |
| 6647464 |
System and method utilizing speculative cache access for improved performance |
Nov. 11, 2003 |
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