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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6804741 |
Coherent memory mapping tables for host I/O bridge |
Oct. 12, 2004 |
| 6801986 |
Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation |
Oct. 5, 2004 |
| 6795850 |
System and method for sharing memory among multiple storage device controllers |
Sep. 21, 2004 |
| 6795896 |
Methods and apparatuses for reducing leakage power consumption in a processor |
Sep. 21, 2004 |
| 6792507 |
Caching system and method for a network storage system |
Sep. 14, 2004 |
| 6792509 |
Partitioned cache of multiple logical levels with adaptive reconfiguration based on multiple criteria |
Sep. 14, 2004 |
| 6792512 |
Method and system for organizing coherence directories in shared memory systems |
Sep. 14, 2004 |
| 6789173 |
Node controller for performing cache coherence control and memory-shared multiprocessor system |
Sep. 7, 2004 |
| 6785773 |
Verification of global coherence in a multi-node NUMA system |
Aug. 31, 2004 |
| 6785774 |
High performance symmetric multiprocessing systems via super-coherent data mechanisms |
Aug. 31, 2004 |
| 6785775 |
Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues |
Aug. 31, 2004 |
| 6785776 |
DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism |
Aug. 31, 2004 |
| 6782456 |
Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism |
Aug. 24, 2004 |
| 6779086 |
Symmetric multiprocessor systems with an independent super-coherent cache directory |
Aug. 17, 2004 |
| 6775748 |
Methods and apparatus for transferring cache block ownership |
Aug. 10, 2004 |
| 6772298 |
Method and apparatus for invalidating a cache line without data return in a multi-node architecture |
Aug. 3, 2004 |
| 6769048 |
Cache synchronization method, system and apparatus for a distributed application and an object located in a client cache |
Jul. 27, 2004 |
| 6766360 |
Caching mechanism for remote read-only data in a cache coherent non-uniform memory access (CCNUMA) architecture |
Jul. 20, 2004 |
| 6766431 |
Data processing system and method for a sector cache |
Jul. 20, 2004 |
| 6763435 |
Super-coherent multiprocessor system bus protocols |
Jul. 13, 2004 |
| 6763436 |
Redundant data storage and data recovery system |
Jul. 13, 2004 |
| 6760786 |
Multiprocessing system configured to perform efficient block copy operations |
Jul. 6, 2004 |
| 6760812 |
System and method for coordinating state between networked caches |
Jul. 6, 2004 |
| 6757786 |
Data consistency memory management system and method and associated multiprocessor network |
Jun. 29, 2004 |
| 6757787 |
Adaptive cache coherence protocols |
Jun. 29, 2004 |
| 6757788 |
CACHE COHERENT CONTROL SYSTEM FOR NETWORK NODES ALLOWS CPU OR I/O DEVICE TO ACCESS TARGET BLOCK WITHOUT CACHE COHERENCE CONTROL, IF ASSOCIATED NODE HAS ACCESS RIGHT IN AN ACCESS RIGHT MEMORY T |
Jun. 29, 2004 |
| 6757790 |
Distributed, scalable data storage facility with cache memory |
Jun. 29, 2004 |
| 6757793 |
Reducing probe traffic in multiprocessor systems using a victim record table |
Jun. 29, 2004 |
| 6754772 |
Distributed cache |
Jun. 22, 2004 |
| 6754782 |
Decentralized global coherency management in a multi-node computer system |
Jun. 22, 2004 |
| 6751710 |
Scalable multiprocessor system and cache coherence method |
Jun. 15, 2004 |
| 6751721 |
Broadcast invalidate scheme |
Jun. 15, 2004 |
| 6748464 |
Semiconductor device comprising CPU and peripheral circuit wherein control unit performs wait cycle control that makes peripheral circuit wait a predetermined time before responding to CPU |
Jun. 8, 2004 |
| 6748490 |
Method and apparatus for maintaining data coherency in a shared memory system |
Jun. 8, 2004 |
| 6748498 |
Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector |
Jun. 8, 2004 |
| 6745294 |
Multi-processor computer system with lock driven cache-flushing system |
Jun. 1, 2004 |
| 6742086 |
Affinity checking process for multiple processor, multiple bus optimization of throughput |
May. 25, 2004 |
| 6738868 |
System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes |
May. 18, 2004 |
| 6735674 |
Method of maintaining data coherency in late-select synchronous pipeline type semiconductor memory device and data coherency maintaining circuit therefor |
May. 11, 2004 |
| 6732239 |
Concurrent access scheme for exclusive mode cache |
May. 4, 2004 |
| 6728818 |
Dual storage adapters utilizing clustered adapters supporting fast write caches |
Apr. 27, 2004 |
| 6728841 |
Conserving system memory bandwidth during a memory read operation in a multiprocessing computer system |
Apr. 27, 2004 |
| 6725334 |
Method and system for exclusive two-level caching in a chip-multiprocessor |
Apr. 20, 2004 |
| 6725340 |
Mechanism for folding storage barrier operations in a multiprocessor system |
Apr. 20, 2004 |
| 6725341 |
Cache line pre-load and pre-own based on cache coherence speculation |
Apr. 20, 2004 |
| 6725342 |
Non-volatile mass storage cache coherency apparatus |
Apr. 20, 2004 |
| 6725343 |
System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system |
Apr. 20, 2004 |
| 6721813 |
Computer system implementing a system and method for tracking the progress of posted write transactions |
Apr. 13, 2004 |
| 6721849 |
Front end system having multiple decoding modes |
Apr. 13, 2004 |
| 6721855 |
Using an L2 directory to facilitate speculative loads in a multiprocessor system |
Apr. 13, 2004 |
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