| |
 |
|
Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6868481 |
Cache coherence protocol for a multiple bus multiprocessor system |
Mar. 15, 2005 |
| 6868483 |
Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment |
Mar. 15, 2005 |
| 6865595 |
Methods and apparatus for speculative probing of a remote cluster |
Mar. 8, 2005 |
| 6865665 |
Processor pipeline cache miss apparatus and method for operation |
Mar. 8, 2005 |
| 6862646 |
Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain |
Mar. 1, 2005 |
| 6862665 |
Method, system, and apparatus for space efficient cache coherency |
Mar. 1, 2005 |
| 6862668 |
Method and apparatus for using cache coherency locking to facilitate on-line volume expansion in a multi-controller storage system |
Mar. 1, 2005 |
| 6862679 |
Synchronization of load operations using load fence instruction in pre-serialization/post-serialization mode |
Mar. 1, 2005 |
| 6862693 |
Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step |
Mar. 1, 2005 |
| 6859863 |
Method and system for managing data at an input/output interface for a multiprocessor system |
Feb. 22, 2005 |
| 6859864 |
Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line |
Feb. 22, 2005 |
| 6857050 |
Data storage system using 3-party hand-off protocol to maintain a single coherent logical image |
Feb. 15, 2005 |
| 6851009 |
Method, system and apparatus for a computer subsystem interconnection using a chain of bus repeaters |
Feb. 1, 2005 |
| 6851024 |
Exclusive caching in computer systems |
Feb. 1, 2005 |
| 6851025 |
Cache management system using cache control instructions for controlling the operation of cache |
Feb. 1, 2005 |
| 6848023 |
Cache directory configuration method and information processing device |
Jan. 25, 2005 |
| 6848032 |
Pipelining cache-coherence operations in a shared-memory multiprocessing system |
Jan. 25, 2005 |
| 6848035 |
Semiconductor device with multi-bank DRAM and cache memory |
Jan. 25, 2005 |
| 6842822 |
System and method for cache external writing |
Jan. 11, 2005 |
| 6842825 |
Adjusting timestamps to preserve update timing information for cached data objects |
Jan. 11, 2005 |
| 6842827 |
Cache coherency arrangement to enhance inbound bandwidth |
Jan. 11, 2005 |
| 6842828 |
Methods and arrangements to enhance an upbound path |
Jan. 11, 2005 |
| 6839788 |
Bus zoning in a channel independent storage controller architecture |
Jan. 4, 2005 |
| 6839806 |
Cache system with a cache tag memory and a cache tag buffer |
Jan. 4, 2005 |
| 6839810 |
Consistency control device merging updated memory blocks |
Jan. 4, 2005 |
| 6839811 |
Semaphore management circuit |
Jan. 4, 2005 |
| 6839816 |
Shared cache line update mechanism |
Jan. 4, 2005 |
| 6836825 |
Method and apparatus for synchronizing caches in a distributed computing system |
Dec. 28, 2004 |
| 6836829 |
Peripheral device interface chip cache and data synchronization method |
Dec. 28, 2004 |
| 6834327 |
Multilevel cache system having unified cache tag memory |
Dec. 21, 2004 |
| 6832282 |
System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system |
Dec. 14, 2004 |
| 6832295 |
Methods and systems for extending an application's address space |
Dec. 14, 2004 |
| 6832297 |
Method and apparatus for managing data in a distributed buffer system |
Dec. 14, 2004 |
| 6829682 |
Destructive read architecture for dynamic random access memories |
Dec. 7, 2004 |
| 6829683 |
System and method for transferring ownership of data in a distributed shared memory system |
Dec. 7, 2004 |
| 6826653 |
Block data mover adapted to contain faults in a partitioned multiprocessor system |
Nov. 30, 2004 |
| 6826654 |
Cache invalidation bus for a highly scalable shared cache memory hierarchy |
Nov. 30, 2004 |
| 6826655 |
Apparatus for imprecisely tracking cache line inclusivity of a higher level cache |
Nov. 30, 2004 |
| 6826656 |
Reducing power in a snooping cache based multiprocessor environment |
Nov. 30, 2004 |
| 6823429 |
Memory controller for controlling memory accesses across networks in distributed shared memory processing systems |
Nov. 23, 2004 |
| 6823430 |
Directoryless L0 cache for stall reduction |
Nov. 23, 2004 |
| 6820174 |
Multi-processor computer system using partition group directories to maintain cache coherence |
Nov. 16, 2004 |
| 6813694 |
Local invalidation buses for a highly scalable shared cache memory hierarchy |
Nov. 2, 2004 |
| 6810259 |
Location update protocol |
Oct. 26, 2004 |
| 6810466 |
Microprocessor and method for performing selective prefetch based on bus activity level |
Oct. 26, 2004 |
| 6810489 |
Checkpoint computer system utilizing a FIFO buffer to re-synchronize and recover the system on the detection of an error |
Oct. 26, 2004 |
| 6807586 |
Increased computer peripheral throughput by using data available withholding |
Oct. 19, 2004 |
| 6807608 |
Multiprocessor environment supporting variable-sized coherency transactions |
Oct. 19, 2004 |
| 6804706 |
Network system for transmitting overwritten portion of client side node cache image to server site through intermediate downstream nodes updating cache images of data requested by client |
Oct. 12, 2004 |
| 6804741 |
Coherent memory mapping tables for host I/O bridge |
Oct. 12, 2004 |
|
|
|
