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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6990657 |
Shared software breakpoints in a shared memory system |
Jan. 24, 2006 |
| 6988170 |
Scalable architecture based on single-chip multiprocessing |
Jan. 17, 2006 |
| 6988172 |
Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status |
Jan. 17, 2006 |
| 6985936 |
Addressing the name space mismatch between content servers and content caching systems |
Jan. 10, 2006 |
| 6986002 |
Adaptive shared data interventions in coupled broadcast engines |
Jan. 10, 2006 |
| 6986005 |
Low latency lock for multiprocessor computer system |
Jan. 10, 2006 |
| 6986011 |
High speed memory cloner within a data processing system |
Jan. 10, 2006 |
| 6983277 |
Method and system of database management for replica database |
Jan. 3, 2006 |
| 6983347 |
Dynamically managing saved processor soft states |
Jan. 3, 2006 |
| 6983353 |
Method and apparatus for enhancing operations in disk array storage devices |
Jan. 3, 2006 |
| 6981097 |
Token based cache-coherence protocol |
Dec. 27, 2005 |
| 6981101 |
Method and system for maintaining data at input/output (I/O) interfaces for a multiprocessor system |
Dec. 27, 2005 |
| 6981102 |
Method and system for managing meta data |
Dec. 27, 2005 |
| 6981103 |
Cache memory control apparatus and processor |
Dec. 27, 2005 |
| 6976128 |
Cache flush system and method |
Dec. 13, 2005 |
| 6976129 |
Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture |
Dec. 13, 2005 |
| 6976131 |
Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system |
Dec. 13, 2005 |
| 6976140 |
Computer system and a method of replication |
Dec. 13, 2005 |
| 6973484 |
Method of communicating data in an interconnect system |
Dec. 6, 2005 |
| 6973543 |
Partial directory cache for reducing probe traffic in multiprocessor systems |
Dec. 6, 2005 |
| 6973544 |
Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system |
Dec. 6, 2005 |
| 6973545 |
System with a directory based coherency protocol and split ownership and access right coherence mechanism |
Dec. 6, 2005 |
| 6973546 |
Method, system, and program for maintaining data in distributed caches |
Dec. 6, 2005 |
| 6973547 |
Coherence message prediction mechanism and multiprocessing computer system employing the same |
Dec. 6, 2005 |
| 6973548 |
Data acceleration mechanism for a multiprocessor shared memory system |
Dec. 6, 2005 |
| 6970979 |
System with virtual address networks and split ownership and access right coherence mechanism |
Nov. 29, 2005 |
| 6970980 |
System with multicast invalidations and split ownership and access right coherence mechanism |
Nov. 29, 2005 |
| 6970981 |
Method and apparatus to maintain consistency between an object store and a plurality of caches utilizing transactional updates to data caches |
Nov. 29, 2005 |
| 6970982 |
Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions |
Nov. 29, 2005 |
| 6968431 |
Method and apparatus for livelock prevention in a multiprocessor system |
Nov. 22, 2005 |
| 6965970 |
List based method and apparatus for selective and rapid cache flushes |
Nov. 15, 2005 |
| 6965972 |
Real time emulation of coherence directories using global sparse directories |
Nov. 15, 2005 |
| 6965973 |
Remote line directory which covers subset of shareable CC-NUMA memory space |
Nov. 15, 2005 |
| 6963953 |
Cache device controlling a state of a corresponding cache memory according to a predetermined protocol |
Nov. 8, 2005 |
| 6961814 |
Disk drive maintaining a cache link attribute for each of a plurality of allocation states |
Nov. 1, 2005 |
| 6961825 |
Cache coherency mechanism using arbitration masks |
Nov. 1, 2005 |
| 6961826 |
Processor state reintegration using bridge direct memory access controller |
Nov. 1, 2005 |
| 6961828 |
Cluster system, memory access control method, and recording medium |
Nov. 1, 2005 |
| 6959364 |
Partially inclusive snoop filter |
Oct. 25, 2005 |
| 6957285 |
Data storage system |
Oct. 18, 2005 |
| 6954829 |
Non-speculative distributed conflict resolution for a cache coherency protocol |
Oct. 11, 2005 |
| 6950906 |
System for and method of operating a cache |
Sep. 27, 2005 |
| 6950909 |
System and method for reducing contention in a multi-sectored cache |
Sep. 27, 2005 |
| 6950913 |
Methods and apparatus for multiple cluster locking |
Sep. 27, 2005 |
| 6948032 |
Method and apparatus for reducing the effects of hot spots in cache memories |
Sep. 20, 2005 |
| 6948033 |
Control method of the cache hierarchy |
Sep. 20, 2005 |
| 6948035 |
Data pend mechanism |
Sep. 20, 2005 |
| 6944719 |
Scalable cache coherent distributed shared memory processing system |
Sep. 13, 2005 |
| 6944721 |
Asynchronous non-blocking snoop invalidation |
Sep. 13, 2005 |
| 6941310 |
System and method for caching data for a mobile application |
Sep. 6, 2005 |
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