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Class Information
Number: 711/141
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Coherency
Description: Subject matter further comprising means or steps not specifically covered above for assuring that the data
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620696 |
System and method for conflict responses in a cache coherency protocol |
Nov. 17, 2009 |
| 7617365 |
Systems and methods to avoid deadlock and guarantee mirror consistency during online mirror synchronization and verification |
Nov. 10, 2009 |
| 7617329 |
Programmable protocol to support coherent and non-coherent transactions in a multinode system |
Nov. 10, 2009 |
| 7613886 |
Methods and apparatus for synchronizing data access to a local memory in a multi-processor system |
Nov. 3, 2009 |
| 7613884 |
Multiprocessor system and method ensuring coherency between a main memory and a cache memory |
Nov. 3, 2009 |
| 7613882 |
Fast invalidation for cache coherency in distributed shared memory system |
Nov. 3, 2009 |
| 7606979 |
Method and system for conservatively managing store capacity available to a processor issuing stores |
Oct. 20, 2009 |
| 7606978 |
Multi-node computer system implementing global access state dependent transactions |
Oct. 20, 2009 |
| 7600149 |
Failure transparency for update applications under single-master configuration |
Oct. 6, 2009 |
| 7600080 |
Avoiding deadlocks in a multiprocessor system |
Oct. 6, 2009 |
| 7600079 |
Performing a memory write of a data unit without changing ownership of the data unit |
Oct. 6, 2009 |
| 7600078 |
Speculatively performing read transactions |
Oct. 6, 2009 |
| 7596712 |
Method and system for efficiently accessing a storage redundancy group |
Sep. 29, 2009 |
| 7596662 |
Selective storage of data in levels of a cache memory |
Sep. 29, 2009 |
| 7596570 |
Data sharing |
Sep. 29, 2009 |
| 7594145 |
Improving performance of a processor having a defective cache |
Sep. 22, 2009 |
| 7590805 |
Monitor implementation in a multicore processor with inclusive LLC |
Sep. 15, 2009 |
| 7587556 |
Store buffer capable of maintaining associated cache information |
Sep. 8, 2009 |
| 7584329 |
Data processing system and method for efficient communication utilizing an Ig coherency state |
Sep. 1, 2009 |
| 7581069 |
Multiple computer system with enhanced memory clean up |
Aug. 25, 2009 |
| 7581068 |
Exclusive ownership snoop filter |
Aug. 25, 2009 |
| 7581064 |
Utilizing cache information to manage memory access and cache utilization |
Aug. 25, 2009 |
| 7581056 |
Load balancing using distributed front end and back end virtualization engines |
Aug. 25, 2009 |
| 7581042 |
I/O hub resident cache line monitor and device register update |
Aug. 25, 2009 |
| RE40877 |
Method of communicating data in an interconnect system |
Aug. 18, 2009 |
| 7577797 |
Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response |
Aug. 18, 2009 |
| 7577795 |
Disowning cache entries on aging out of the entry |
Aug. 18, 2009 |
| 7577794 |
Low latency coherency protocol for a multi-chip multiprocessor system |
Aug. 18, 2009 |
| 7574571 |
Hardware-based encryption/decryption employing dual ported memory and fast table initialization |
Aug. 11, 2009 |
| 7574567 |
Monitoring processes in a non-uniform memory access (NUMA) computer system |
Aug. 11, 2009 |
| 7574566 |
System and method for efficient software cache coherence |
Aug. 11, 2009 |
| 7571288 |
Scalable rundown protection for object lifetime management |
Aug. 4, 2009 |
| 7571286 |
Reduced memory traffic via detection and tracking of temporally silent stores |
Aug. 4, 2009 |
| 7571285 |
Data classification in shared cache of multiple-core processor |
Aug. 4, 2009 |
| 7568072 |
Cache eviction |
Jul. 28, 2009 |
| 7562192 |
Microprocessor, apparatus and method for selective prefetch retire |
Jul. 14, 2009 |
| 7558913 |
Atomic commit of cache transfer with staging area |
Jul. 7, 2009 |
| 7552295 |
Maintaining consistency when mirroring data using different copy technologies |
Jun. 23, 2009 |
| 7552288 |
Selectively inclusive cache architecture |
Jun. 23, 2009 |
| 7552247 |
Increased computer peripheral throughput by using data available withholding |
Jun. 23, 2009 |
| 7552223 |
Apparatus and method for data consistency in a proxy cache |
Jun. 23, 2009 |
| 7549025 |
Efficient marking of shared cache lines |
Jun. 16, 2009 |
| 7549024 |
Multi-processing system with coherent and non-coherent modes |
Jun. 16, 2009 |
| 7548918 |
Techniques for maintaining consistency for different requestors of files in a database management system |
Jun. 16, 2009 |
| 7546422 |
Method and apparatus for the synchronization of distributed caches |
Jun. 9, 2009 |
| 7546421 |
Interconnect transaction translation technique |
Jun. 9, 2009 |
| 7543121 |
Computer system allowing any computer to copy any storage area within a storage system |
Jun. 2, 2009 |
| 7543116 |
Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains |
Jun. 2, 2009 |
| 7543115 |
Two-hop source snoop based cache coherence protocol |
Jun. 2, 2009 |
| 7539823 |
Multiprocessing apparatus having reduced cache miss occurrences |
May. 26, 2009 |
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