| Patent Number |
Title Of Patent |
Date Issued |
| 7617329 |
Programmable protocol to support coherent and non-coherent transactions in a multinode system |
Nov. 10, 2009 |
| 7594080 |
Temporary storage of memory line while waiting for cache eviction |
Sep. 22, 2009 |
| RE40921 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system |
Sep. 22, 2009 |
| 7571283 |
Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch |
Aug. 4, 2009 |
| 7552287 |
Method and system of controlling a cache memory by interrupting prefetch request with a demand fetch request |
Jun. 23, 2009 |
| 7543115 |
Two-hop source snoop based cache coherence protocol |
Jun. 2, 2009 |
| 7543120 |
Processor and data processing system employing a variable store gather window |
Jun. 2, 2009 |
| 7536509 |
Method for fetching data from a non-volatile memory in an integrated circuit and corresponding integrated circuit |
May. 19, 2009 |
| 7526702 |
Method and system for testing a random access memory (RAM) device having an internal cache |
Apr. 28, 2009 |
| 7502892 |
Decoupling request for ownership tag reads from data read operations |
Mar. 10, 2009 |
| 7493621 |
Context switch data prefetching in multithreaded computer |
Feb. 17, 2009 |
| 7487317 |
Cache-aware scheduling for a chip multithreading processor |
Feb. 3, 2009 |
| 7475210 |
Data stream generation method for enabling high-speed memory access |
Jan. 6, 2009 |
| 7464242 |
Method of load/store dependencies detection with dynamically changing address length |
Dec. 9, 2008 |
| 7447845 |
Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality |
Nov. 4, 2008 |
| 7447844 |
Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule |
Nov. 4, 2008 |
| 7447807 |
Systems and methods for storing data in segments of a storage subsystem |
Nov. 4, 2008 |
| 7401189 |
Pipelining D states for MRU steerage during MRU/LRU member allocation |
Jul. 15, 2008 |
| 7398358 |
Method and apparatus for high performance branching in pipelined microsystems |
Jul. 8, 2008 |
| 7376793 |
Cache coherence protocol with speculative writestream |
May. 20, 2008 |
| 7370150 |
System and method for managing a cache memory |
May. 6, 2008 |
| 7363468 |
Load address dependency mechanism system and method in a high frequency, low power processor system |
Apr. 22, 2008 |
| 7353310 |
Hierarchical memory access via pipelining with deferred arbitration |
Apr. 1, 2008 |
| 7302527 |
Systems and methods for executing load instructions that avoid order violations |
Nov. 27, 2007 |
| 7269179 |
Control mechanisms for enqueue and dequeue operations in a pipelined network processor |
Sep. 11, 2007 |
| 7263585 |
Store-induced instruction coherency mechanism |
Aug. 28, 2007 |
| 7243192 |
Cache memory architecture with system controller device that compares cache tags to memory addresses received from microprocessor |
Jul. 10, 2007 |
| 7243203 |
Pipeline circuit for low latency memory |
Jul. 10, 2007 |
| 7234027 |
Instructions for test & set with selectively enabled cache invalidate |
Jun. 19, 2007 |
| 7225300 |
Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system |
May. 29, 2007 |
| 7206230 |
Use of data latches in cache operations of non-volatile memories |
Apr. 17, 2007 |
| 7197603 |
Method and apparatus for high performance branching in pipelined microsystems |
Mar. 27, 2007 |
| 7181575 |
Instruction cache using single-ported memories |
Feb. 20, 2007 |
| 7177987 |
System and method for responses between different cache coherency protocols |
Feb. 13, 2007 |
| 7171535 |
Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline |
Jan. 30, 2007 |
| 7162618 |
Method for enhancing the visibility of effective address computation in pipelined architectures |
Jan. 9, 2007 |
| 7155574 |
Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory |
Dec. 26, 2006 |
| 7146468 |
Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache |
Dec. 5, 2006 |
| 7143240 |
System and method for providing a cost-adaptive cache |
Nov. 28, 2006 |
| 7133968 |
Method and apparatus for resolving additional load misses in a single pipeline processor under stalls of instructions not accessing memory-mapped I/O regions |
Nov. 7, 2006 |
| 7130968 |
Cache memory architecture and associated microprocessor design |
Oct. 31, 2006 |
| 7124262 |
Selectivity pipelining and prefetching memory data |
Oct. 17, 2006 |
| 7111127 |
System for supporting unlimited consecutive data stores into a cache memory |
Sep. 19, 2006 |
| 7085885 |
Apparatus and method for early cache miss detection |
Aug. 1, 2006 |
| 7073026 |
Microprocessor including cache memory supporting multiple accesses per cycle |
Jul. 4, 2006 |
| 7047317 |
High performance network address processor system |
May. 16, 2006 |
| 7039762 |
Parallel cache interleave accesses with address-sliced directories |
May. 2, 2006 |
| 7028141 |
High-speed distributed data processing system and method |
Apr. 11, 2006 |
| 7013366 |
Parallel search technique for store operations |
Mar. 14, 2006 |
| 7003645 |
Use of a storage medium as a communications network for liveness determination in a high-availability cluster |
Feb. 21, 2006 |
