| |
 |
|
Class Information
Number: 711/131
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Multiport cache
Description: Subject matter further comprising caches composed of multiport memory
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620780 |
Multiprocessor system with cache controlled scatter-gather operations |
Nov. 17, 2009 |
| 7620954 |
Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors |
Nov. 17, 2009 |
| 7617329 |
Programmable protocol to support coherent and non-coherent transactions in a multinode system |
Nov. 10, 2009 |
| 7613886 |
Methods and apparatus for synchronizing data access to a local memory in a multi-processor system |
Nov. 3, 2009 |
| 7613065 |
Multi-port memory device |
Nov. 3, 2009 |
| 7606807 |
Method and apparatus to utilize free cache in a storage system |
Oct. 20, 2009 |
| 7603523 |
Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture |
Oct. 13, 2009 |
| 7577015 |
Memory content inverting to minimize NTBI effects |
Aug. 18, 2009 |
| 7571281 |
Look-up filter structures, systems and methods for filtering accesses to a pool of tags for cache memories |
Aug. 4, 2009 |
| 7562193 |
Memory with single and dual mode access |
Jul. 14, 2009 |
| 7536400 |
Write-back to cells |
May. 19, 2009 |
| 7536499 |
Memory access control device and processing system having same |
May. 19, 2009 |
| 7536512 |
Method and apparatus for space efficient identification of candidate objects for eviction from a large cache |
May. 19, 2009 |
| 7529139 |
N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof |
May. 5, 2009 |
| 7526612 |
Multiport cache memory which reduces probability of bank contention and access control system thereof |
Apr. 28, 2009 |
| 7519770 |
Disk array control device with an internal connection system for efficient data transfer |
Apr. 14, 2009 |
| 7519779 |
Dumping using limited system address space |
Apr. 14, 2009 |
| 7467261 |
Dual storage apparatus and control method for the dual storage apparatus |
Dec. 16, 2008 |
| 7447812 |
Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files |
Nov. 4, 2008 |
| 7421559 |
Apparatus and method for a synchronous multi-port memory |
Sep. 2, 2008 |
| 7401186 |
System and method for tracking changes in L1 data cache directory |
Jul. 15, 2008 |
| 7363430 |
Determination of cache entry for future operation |
Apr. 22, 2008 |
| 7360024 |
Multi-port integrated cache |
Apr. 15, 2008 |
| 7346739 |
First-in-first-out memory system and method for providing same |
Mar. 18, 2008 |
| 7340562 |
Cache for instruction set architecture |
Mar. 4, 2008 |
| 7337372 |
Method and apparatus for detecting multi-hit errors in a cache |
Feb. 26, 2008 |
| 7320053 |
Banking render cache for multiple access |
Jan. 15, 2008 |
| 7318122 |
Disk array control device with an internal connection system for efficient data transfer |
Jan. 8, 2008 |
| 7307912 |
Variable data width memory systems and methods |
Dec. 11, 2007 |
| 7234022 |
Cache accumulator memory for performing operations on block operands |
Jun. 19, 2007 |
| 7219185 |
Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache |
May. 15, 2007 |
| 7216206 |
Control apparatus of storage unit, and method of controlling the control apparatus of storage unit |
May. 8, 2007 |
| 7213104 |
Disk array control device with an internal connection system for efficient data transfer |
May. 1, 2007 |
| 7194581 |
Memory channel with hot add/remove |
Mar. 20, 2007 |
| 7178000 |
Trace buffer for DDR memories |
Feb. 13, 2007 |
| 7162591 |
Processor memory having a dedicated port |
Jan. 9, 2007 |
| 7152138 |
System on a chip having a non-volatile imperfect memory |
Dec. 19, 2006 |
| 7142541 |
Determining routing information for an information packet in accordance with a destination address and a device address |
Nov. 28, 2006 |
| 7124236 |
Microprocessor including bank-pipelined cache with asynchronous data blocks |
Oct. 17, 2006 |
| 7124250 |
Memory module device for use in high-frequency operation |
Oct. 17, 2006 |
| 7120080 |
Dual port semiconductor memory device |
Oct. 10, 2006 |
| 7114041 |
AMBA modular memory controller |
Sep. 26, 2006 |
| 7111131 |
Control apparatus of storage unit, and method of controlling the control apparatus of storage unit |
Sep. 19, 2006 |
| 7095674 |
Modular register array |
Aug. 22, 2006 |
| 7076610 |
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same |
Jul. 11, 2006 |
| 7073026 |
Microprocessor including cache memory supporting multiple accesses per cycle |
Jul. 4, 2006 |
| 7057911 |
Memory structure, a system, and an electronic device, as well as a method in connection with a memory circuit |
Jun. 6, 2006 |
| 7042792 |
Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays |
May. 9, 2006 |
| 7020752 |
Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory unit |
Mar. 28, 2006 |
| 7016912 |
Write-back to cells |
Mar. 21, 2006 |
|
|
|
