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Class Information
Number: 711/125
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Instruction data cache
Description: Subject matter further comprising means or steps using a single cache dedicated to caching instruction data
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7613894 |
Power loss recovery in non-volatile memory |
Nov. 3, 2009 |
| 7610433 |
Memory controller interface |
Oct. 27, 2009 |
| 7610449 |
Apparatus and method for saving power in a trace cache |
Oct. 27, 2009 |
| 7606975 |
Trace cache for efficient self-modifying code processing |
Oct. 20, 2009 |
| 7587566 |
Realtime memory management via locking realtime threads and related data structures |
Sep. 8, 2009 |
| 7587555 |
Program thread synchronization |
Sep. 8, 2009 |
| 7568112 |
Data access control method for tamper resistant microprocessor using cache memory |
Jul. 28, 2009 |
| 7568076 |
Variable store gather window |
Jul. 28, 2009 |
| 7568070 |
Instruction cache having fixed number of variable length instructions |
Jul. 28, 2009 |
| 7555607 |
Program thread syncronization for instruction cachelines |
Jun. 30, 2009 |
| 7552283 |
Efficient memory hierarchy management |
Jun. 23, 2009 |
| 7543120 |
Processor and data processing system employing a variable store gather window |
Jun. 2, 2009 |
| 7543127 |
Computer system |
Jun. 2, 2009 |
| 7529889 |
Data processing apparatus and method for performing a cache lookup in an energy efficient manner |
May. 5, 2009 |
| 7523266 |
Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level |
Apr. 21, 2009 |
| 7523261 |
Method and circuit arrangement for adapting a program to suit a buffer store |
Apr. 21, 2009 |
| 7500066 |
Method and apparatus for sharing instruction memory among a plurality of processors |
Mar. 3, 2009 |
| 7493447 |
System and method for caching sequential programs |
Feb. 17, 2009 |
| 7493621 |
Context switch data prefetching in multithreaded computer |
Feb. 17, 2009 |
| 7478198 |
Multithreaded clustered microarchitecture with dynamic back-end assignment |
Jan. 13, 2009 |
| 7478199 |
Cache coloring based on dynamic function flow |
Jan. 13, 2009 |
| 7469332 |
Systems and methods for adaptively mapping an instruction cache |
Dec. 23, 2008 |
| 7461205 |
Performing useful computations while waiting for a line in a system with a software implemented cache |
Dec. 2, 2008 |
| 7456835 |
Register based queuing for texture requests |
Nov. 25, 2008 |
| 7454570 |
Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor |
Nov. 18, 2008 |
| 7437537 |
Methods and apparatus for predicting unaligned memory access |
Oct. 14, 2008 |
| 7437512 |
Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions |
Oct. 14, 2008 |
| 7427990 |
Data replacement method and circuit for motion prediction cache |
Sep. 23, 2008 |
| 7426626 |
TLB lock indicator |
Sep. 16, 2008 |
| 7426612 |
Methods and apparatus for enforcing instruction-cache coherence |
Sep. 16, 2008 |
| 7421684 |
Method and apparatus for autonomic test case feedback using hardware assistance for data coverage |
Sep. 2, 2008 |
| 7418552 |
Memory disambiguation for large instruction windows |
Aug. 26, 2008 |
| 7414517 |
Radio frequency identification transponder |
Aug. 19, 2008 |
| 7406569 |
Instruction cache way prediction for jump targets |
Jul. 29, 2008 |
| 7404042 |
Handling cache miss in an instruction crossing a cache line boundary |
Jul. 22, 2008 |
| 7401184 |
Matching memory transactions to cache line boundaries |
Jul. 15, 2008 |
| 7389385 |
Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis |
Jun. 17, 2008 |
| 7386670 |
Processing of self-modifying code in multi-address-space and multi-processor systems |
Jun. 10, 2008 |
| 7383403 |
Concurrent bypass to instruction buffers in a fine grain multithreaded processor |
Jun. 3, 2008 |
| 7366885 |
Method for optimizing loop control of microcoded instructions |
Apr. 29, 2008 |
| 7366875 |
Method and apparatus for an efficient multi-path trace cache design |
Apr. 29, 2008 |
| 7366851 |
Processor, method, and data processing system employing a variable store gather window |
Apr. 29, 2008 |
| 7363428 |
Microprocessor with hot routine memory and method of operation |
Apr. 22, 2008 |
| 7363468 |
Load address dependency mechanism system and method in a high frequency, low power processor system |
Apr. 22, 2008 |
| 7355601 |
System and method for transfer of data between processors using a locked set, head and tail pointers |
Apr. 8, 2008 |
| 7356456 |
Computer storage exception handing apparatus and method for virtual hardware system |
Apr. 8, 2008 |
| 7353513 |
Method and apparatus for establishing a bound on the effect of task interference in a cache memory |
Apr. 1, 2008 |
| 7353445 |
Cache error handling in a multithreaded/multi-core processor |
Apr. 1, 2008 |
| 7353337 |
Reducing cache effects of certain code pieces |
Apr. 1, 2008 |
| 7346737 |
Cache system having branch target address cache |
Mar. 18, 2008 |
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