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Class Information
Number: 711/125
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Instruction data cache
Description: Subject matter further comprising means or steps using a single cache dedicated to caching instruction data
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7427990 |
Data replacement method and circuit for motion prediction cache |
Sep. 23, 2008 |
| 7426612 |
Methods and apparatus for enforcing instruction-cache coherence |
Sep. 16, 2008 |
| 7426626 |
TLB lock indicator |
Sep. 16, 2008 |
| 7421684 |
Method and apparatus for autonomic test case feedback using hardware assistance for data coverage |
Sep. 2, 2008 |
| 7418552 |
Memory disambiguation for large instruction windows |
Aug. 26, 2008 |
| 7414517 |
Radio frequency identification transponder |
Aug. 19, 2008 |
| 7406569 |
Instruction cache way prediction for jump targets |
Jul. 29, 2008 |
| 7404042 |
Handling cache miss in an instruction crossing a cache line boundary |
Jul. 22, 2008 |
| 7401184 |
Matching memory transactions to cache line boundaries |
Jul. 15, 2008 |
| 7389385 |
Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis |
Jun. 17, 2008 |
| 7386670 |
Processing of self-modifying code in multi-address-space and multi-processor systems |
Jun. 10, 2008 |
| 7383403 |
Concurrent bypass to instruction buffers in a fine grain multithreaded processor |
Jun. 3, 2008 |
| 7366851 |
Processor, method, and data processing system employing a variable store gather window |
Apr. 29, 2008 |
| 7366875 |
Method and apparatus for an efficient multi-path trace cache design |
Apr. 29, 2008 |
| 7366885 |
Method for optimizing loop control of microcoded instructions |
Apr. 29, 2008 |
| 7363428 |
Microprocessor with hot routine memory and method of operation |
Apr. 22, 2008 |
| 7363468 |
Load address dependency mechanism system and method in a high frequency, low power processor system |
Apr. 22, 2008 |
| 7355601 |
System and method for transfer of data between processors using a locked set, head and tail pointers |
Apr. 8, 2008 |
| 7356456 |
Computer storage exception handing apparatus and method for virtual hardware system |
Apr. 8, 2008 |
| 7353337 |
Reducing cache effects of certain code pieces |
Apr. 1, 2008 |
| 7353445 |
Cache error handling in a multithreaded/multi-core processor |
Apr. 1, 2008 |
| 7353513 |
Method and apparatus for establishing a bound on the effect of task interference in a cache memory |
Apr. 1, 2008 |
| 7346741 |
Memory latency of processors with configurable stride based pre-fetching technique |
Mar. 18, 2008 |
| 7346737 |
Cache system having branch target address cache |
Mar. 18, 2008 |
| 7340564 |
Tracing instruction flow in an integrated processor |
Mar. 4, 2008 |
| 7337272 |
Method and apparatus for caching variable length instructions |
Feb. 26, 2008 |
| 7315918 |
Processor block placement relative to memory in a programmable logic device |
Jan. 1, 2008 |
| 7302527 |
Systems and methods for executing load instructions that avoid order violations |
Nov. 27, 2007 |
| 7299319 |
Method and apparatus for providing hardware assistance for code coverage |
Nov. 20, 2007 |
| 7287123 |
Cache memory, system, and method of storing data |
Oct. 23, 2007 |
| 7278013 |
Apparatus having a cache and a loop buffer |
Oct. 2, 2007 |
| 7263585 |
Store-induced instruction coherency mechanism |
Aug. 28, 2007 |
| 7260684 |
Trace cache filtering |
Aug. 21, 2007 |
| 7249352 |
Apparatus and method for removing elements from a linked list |
Jul. 24, 2007 |
| 7237064 |
Method and apparatus for feedback-based management of combined heap and compiled code caches |
Jun. 26, 2007 |
| 7234025 |
Microprocessor with repeat prefetch instruction |
Jun. 19, 2007 |
| 7228385 |
Processor, data processing system and method for synchronizing access to data in shared memory |
Jun. 5, 2007 |
| 7222218 |
System and method for goal-based scheduling of blocks of code for concurrent execution |
May. 22, 2007 |
| 7203799 |
Invalidation of instruction cache line during reset handling |
Apr. 10, 2007 |
| 7200717 |
Processor, data processing system and method for synchronizing access to data in shared memory |
Apr. 3, 2007 |
| 7197604 |
Processor, data processing system and method for synchronzing access to data in shared memory |
Mar. 27, 2007 |
| 7197603 |
Method and apparatus for high performance branching in pipelined microsystems |
Mar. 27, 2007 |
| 7194576 |
Fetch operations in a disk drive control system |
Mar. 20, 2007 |
| 7181575 |
Instruction cache using single-ported memories |
Feb. 20, 2007 |
| 7181598 |
Prediction of load-store dependencies in a processing agent |
Feb. 20, 2007 |
| 7177982 |
Method to maintain order between multiple queues with different ordering requirements in a high frequency system |
Feb. 13, 2007 |
| 7162585 |
Semiconductor memory device storing part of program designated by programmer, and software development apparatus for system using the same |
Jan. 9, 2007 |
| 7143393 |
Method for cache management for positioning cache slot |
Nov. 28, 2006 |
| 7142541 |
Determining routing information for an information packet in accordance with a destination address and a device address |
Nov. 28, 2006 |
| 7133969 |
System and method for handling exceptional instructions in a trace cache based processor |
Nov. 7, 2006 |
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