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Class Information
Number: 711/121
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Hierarchical memories > Caching > Multiple caches > Private caches
Description: Subject matter further comprising means or steps for employing plural cache memories where at least one of the caches is exclusively associated with a respective one of a plurality of processors
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7404046 |
Cache memory, processing unit, data processing system and method for filtering snooped operations |
Jul. 22, 2008 |
| 7404041 |
Low complexity speculative multithreading system based on unmodified microprocessor core |
Jul. 22, 2008 |
| 7398360 |
Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors |
Jul. 8, 2008 |
| 7392345 |
Policy setting for client-side caching |
Jun. 24, 2008 |
| 7392346 |
Memory updater using a control array to defer memory operations |
Jun. 24, 2008 |
| 7350027 |
Architectural support for thread level speculative execution |
Mar. 25, 2008 |
| 7346738 |
Cache memory for a scalable information distribution system |
Mar. 18, 2008 |
| 7305522 |
Victim cache using direct intervention |
Dec. 4, 2007 |
| 7305523 |
Cache memory direct intervention |
Dec. 4, 2007 |
| 7246205 |
Software controlled dynamic push cache |
Jul. 17, 2007 |
| 7240143 |
Data access and address translation for retrieval of data amongst multiple interconnected access nodes |
Jul. 3, 2007 |
| 7213107 |
Dedicated cache memory |
May. 1, 2007 |
| 7200718 |
Cache memory for a scalable information distribution system |
Apr. 3, 2007 |
| 7181539 |
System and method for data synchronization |
Feb. 20, 2007 |
| 7174431 |
Mechanism for resolving ambiguous invalidates in a computer system |
Feb. 6, 2007 |
| 7142541 |
Determining routing information for an information packet in accordance with a destination address and a device address |
Nov. 28, 2006 |
| 7114156 |
System and method for processing multiple work flow requests from multiple users in a queuing system |
Sep. 26, 2006 |
| 7086056 |
Processor unit for executing event processes in real time without causing process interference |
Aug. 1, 2006 |
| 7076613 |
Cache line pre-load and pre-own based on cache coherence speculation |
Jul. 11, 2006 |
| 7062606 |
Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events |
Jun. 13, 2006 |
| 7058770 |
Method and apparatus for controlling the recording of digital information, by using unit management table |
Jun. 6, 2006 |
| 7000073 |
Buffer controller and management method thereof |
Feb. 14, 2006 |
| 6996678 |
Method and apparatus for randomized cache entry replacement |
Feb. 7, 2006 |
| 6996657 |
Apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system |
Feb. 7, 2006 |
| 6990559 |
Mechanism for resolving ambiguous invalidates in a computer system |
Jan. 24, 2006 |
| 6986018 |
Method and apparatus for selecting cache and proxy policy |
Jan. 10, 2006 |
| 6985999 |
Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests |
Jan. 10, 2006 |
| 6973539 |
Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords |
Dec. 6, 2005 |
| 6963953 |
Cache device controlling a state of a corresponding cache memory according to a predetermined protocol |
Nov. 8, 2005 |
| 6957313 |
Memory matrix and method of operating the same |
Oct. 18, 2005 |
| 6950908 |
Speculative cache memory control method and multi-processor system |
Sep. 27, 2005 |
| 6948010 |
Method and apparatus for efficiently moving portions of a memory block |
Sep. 20, 2005 |
| 6871268 |
Methods and systems for distributed caching in presence of updates and in accordance with holding times |
Mar. 22, 2005 |
| 6868483 |
Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment |
Mar. 15, 2005 |
| 6865649 |
Method and apparatus for pre-fetching data during program execution |
Mar. 8, 2005 |
| 6859864 |
Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line |
Feb. 22, 2005 |
| 6857052 |
Multi-processor system including a mode switching controller |
Feb. 15, 2005 |
| 6820186 |
System and method for building packets |
Nov. 16, 2004 |
| 6799247 |
Remote memory processor architecture |
Sep. 28, 2004 |
| 6795905 |
Controlling accesses to isolated memory using a memory controller for isolated execution |
Sep. 21, 2004 |
| 6766360 |
Caching mechanism for remote read-only data in a cache coherent non-uniform memory access (CCNUMA) architecture |
Jul. 20, 2004 |
| 6766447 |
System and method of preventing speculative reading during memory initialization |
Jul. 20, 2004 |
| 6760811 |
Gateword acquisition in a multiprocessor write-into-cache environment |
Jul. 6, 2004 |
| 6757785 |
Method and system for improving cache performance in a multiprocessor computer |
Jun. 29, 2004 |
| 6754774 |
Streaming output engine facilitating data transfers between application engines and memory |
Jun. 22, 2004 |
| 6745310 |
Real time local and remote management of data files and directories and method of operating the same |
Jun. 1, 2004 |
| 6675277 |
Method and apparatus for demand usable adapter memory access management |
Jan. 6, 2004 |
| 6675261 |
Request based caching of data store data |
Jan. 6, 2004 |
| 6662272 |
Dynamic cache partitioning |
Dec. 9, 2003 |
| 6611898 |
Object-oriented cache management system and method |
Aug. 26, 2003 |
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