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Class Information
Number: 711/109
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Specific memory composition > Shift register memory
Description: Subject matter including memory
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7421559 |
Apparatus and method for a synchronous multi-port memory |
Sep. 2, 2008 |
| 7409717 |
Metamorphic computer virus detection |
Aug. 5, 2008 |
| 7392417 |
Device for exchanging data signals between two clock domains |
Jun. 24, 2008 |
| 7346739 |
First-in-first-out memory system and method for providing same |
Mar. 18, 2008 |
| 7334063 |
Method and device for register access according to identifier register |
Feb. 19, 2008 |
| 7287169 |
Electronic device and timer therefor with tamper event stamp features and related methods |
Oct. 23, 2007 |
| 7266650 |
Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts |
Sep. 4, 2007 |
| 7254670 |
System, method, and apparatus for realizing quicker access of an element in a data structure |
Aug. 7, 2007 |
| 7200724 |
Two dimensional data access in a processor |
Apr. 3, 2007 |
| 7174014 |
Method and system for performing permutations with bit permutation instructions |
Feb. 6, 2007 |
| 7165143 |
System and method for manipulating cache data |
Jan. 16, 2007 |
| 7162573 |
Communication registers for processing elements |
Jan. 9, 2007 |
| 7162608 |
Translation lookaside buffer-based memory system and method for use in a computer having a plurality of processor element |
Jan. 9, 2007 |
| 7152153 |
Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction |
Dec. 19, 2006 |
| 7148826 |
Data input circuit and semiconductor device utilizing data input circuit |
Dec. 12, 2006 |
| 7130857 |
Method for accessing a memory unit in which sequences of notes are stored, corresponding memory unit and corresponding program |
Oct. 31, 2006 |
| 7126601 |
Graphics memory system that utilizes detached-Z buffering in conjunction with a batching architecture to reduce paging overhead |
Oct. 24, 2006 |
| 7120744 |
System and method for managing a cache memory |
Oct. 10, 2006 |
| 7117316 |
Memory hub and access method having internal row caching |
Oct. 3, 2006 |
| 7107393 |
Systems and method for transferring data asynchronously between clock domains |
Sep. 12, 2006 |
| 7103719 |
System and method for managing a cache memory |
Sep. 5, 2006 |
| 7095742 |
Packet processing unit |
Aug. 22, 2006 |
| 7092301 |
Controller and method for writing data |
Aug. 15, 2006 |
| 7093084 |
Memory implementations of shift registers |
Aug. 15, 2006 |
| 7080216 |
Data access in a processor |
Jul. 18, 2006 |
| 7073019 |
Method and apparatus for assembling non-aligned packet fragments over multiple cycles |
Jul. 4, 2006 |
| 7051153 |
Memory array operating as a shift register |
May. 23, 2006 |
| 7028149 |
System and method for resetting a platform configuration register |
Apr. 11, 2006 |
| 6996665 |
Hazard queue for transaction pipeline |
Feb. 7, 2006 |
| 6986089 |
Power reduction in scannable D-flip-flop with synchronous preset or clear |
Jan. 10, 2006 |
| 6985993 |
Control register assembly |
Jan. 10, 2006 |
| 6978344 |
Shift register control of a circular elasticity buffer |
Dec. 20, 2005 |
| 6957309 |
Method and apparatus for re-accessing a FIFO location |
Oct. 18, 2005 |
| 6952756 |
Method and apparatus for speculative loading of a memory |
Oct. 4, 2005 |
| 6948030 |
FIFO memory system and method |
Sep. 20, 2005 |
| 6941418 |
Integrated circuit and method outputting data |
Sep. 6, 2005 |
| 6941438 |
Memory interleaving |
Sep. 6, 2005 |
| 6920595 |
Skewed latch flip-flop with embedded scan function |
Jul. 19, 2005 |
| 6920526 |
Dual-bank FIFO for synchronization of read data in DDR SDRAM |
Jul. 19, 2005 |
| 6901490 |
Read/modify/write registers |
May. 31, 2005 |
| 6886048 |
Techniques for processing out-of-order requests in a processor-based system |
Apr. 26, 2005 |
| 6882656 |
Speculative transmit for system area network latency reduction |
Apr. 19, 2005 |
| 6857043 |
Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter |
Feb. 15, 2005 |
| 6836837 |
Register addressing |
Dec. 28, 2004 |
| 6829716 |
Latch structure for interlocked pipelined CMOS (IPCMOS) circuits |
Dec. 7, 2004 |
| 6826354 |
Buffer control method and buffer control device |
Nov. 30, 2004 |
| 6813658 |
Dynamic data queuing mechanism for packet networks |
Nov. 2, 2004 |
| 6804743 |
Two step memory device command buffer apparatus and method and memory devices and computer systems using same |
Oct. 12, 2004 |
| 6765922 |
Speculative transmit for system area network latency reduction |
Jul. 20, 2004 |
| 6766411 |
Circuit for looping serial bit streams from parallel memory |
Jul. 20, 2004 |
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