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Class Information
Number: 711/105
Name: Electrical computers and digital processing systems: memory > Storage accessing and control > Specific memory composition > Solid-state random access memory (ram) > Dynamic random access memory
Description: Subject matter including means or steps for accessing volatile memory
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620789 |
Out of order DRAM sequencer |
Nov. 17, 2009 |
| 7619379 |
Motor control device and setting method thereof |
Nov. 17, 2009 |
| 7619912 |
Memory module decoder |
Nov. 17, 2009 |
| 7620770 |
Device and method for storing and processing data units |
Nov. 17, 2009 |
| 7620783 |
Method and apparatus for obtaining memory status information cross-reference to related applications |
Nov. 17, 2009 |
| 7617354 |
Abbreviated burst data transfers for semiconductor memory |
Nov. 10, 2009 |
| 7616470 |
Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom |
Nov. 10, 2009 |
| 7617355 |
Parity-scanning and refresh in dynamic memory devices |
Nov. 10, 2009 |
| 7613892 |
Recording device, recording method, recording medium, and program |
Nov. 3, 2009 |
| 7613883 |
Memory device with mode-selectable prefetch and clock-to-core timing |
Nov. 3, 2009 |
| 7613880 |
Memory module, memory system, and information device |
Nov. 3, 2009 |
| 7613873 |
Deferring refreshes during calibrations in memory systems |
Nov. 3, 2009 |
| 7613866 |
Method for controlling access to a multibank memory |
Nov. 3, 2009 |
| 7606970 |
Hybrid disk drive and method of controlling data therein |
Oct. 20, 2009 |
| 7606988 |
Systems and methods for providing a dynamic memory bank page policy |
Oct. 20, 2009 |
| 7603493 |
Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction |
Oct. 13, 2009 |
| 7600065 |
Arbitration scheme for shared memory device |
Oct. 6, 2009 |
| 7596707 |
System and method for efficient power throttling in multiprocessor chip |
Sep. 29, 2009 |
| 7594068 |
System and method for persistent RAM disk |
Sep. 22, 2009 |
| 7594066 |
Storage system comprising non-volatile memory devices with internal and external refresh processing |
Sep. 22, 2009 |
| 7590797 |
System and method for optimizing interconnections of components in a multichip memory module |
Sep. 15, 2009 |
| 7587547 |
Dynamic update adaptive idle timer |
Sep. 8, 2009 |
| 7583732 |
Managing bursts of data |
Sep. 1, 2009 |
| 7584321 |
Memory address and datapath multiplexing |
Sep. 1, 2009 |
| 7581070 |
Multi-chip package device having alternately-enabled memory chips |
Aug. 25, 2009 |
| 7581076 |
Methods and devices for treating and/or processing data |
Aug. 25, 2009 |
| 7577814 |
Firmware memory management |
Aug. 18, 2009 |
| 7574616 |
Memory device having a power down exit register |
Aug. 11, 2009 |
| 7574555 |
Memory system having daisy chained memory controllers |
Aug. 11, 2009 |
| 7571296 |
Memory controller-adaptive 1T/2T timing control |
Aug. 4, 2009 |
| 7565480 |
Dynamic memory supporting simultaneous refresh and data-access transactions |
Jul. 21, 2009 |
| 7562178 |
Memory hub and method for memory sequencing |
Jul. 14, 2009 |
| 7562184 |
DRAM controller for graphics processing operable to enable/disable burst transfer |
Jul. 14, 2009 |
| 7562193 |
Memory with single and dual mode access |
Jul. 14, 2009 |
| 7558127 |
Data output circuit and method in DDR synchronous semiconductor device |
Jul. 7, 2009 |
| 7558908 |
Structure of sequencers that perform initial and periodic calibrations in a memory system |
Jul. 7, 2009 |
| 7558932 |
Semiconductor memory device and method for operating the same |
Jul. 7, 2009 |
| 7558933 |
Synchronous dynamic random access memory interface and method |
Jul. 7, 2009 |
| 7549001 |
Digital RAM memory circuit with an expanded command structure |
Jun. 16, 2009 |
| 7549034 |
Redistribution of memory to reduce computer system power consumption |
Jun. 16, 2009 |
| 7543105 |
Memory access control based on hit prediction |
Jun. 2, 2009 |
| 7539812 |
System and method to increase DRAM parallelism |
May. 26, 2009 |
| 7536519 |
Memory access control apparatus and method for accomodating effects of signal delays caused by load |
May. 19, 2009 |
| 7536530 |
Method and apparatus for determining a dynamic random access memory page management implementation |
May. 19, 2009 |
| 7533212 |
System memory board subsystem using DRAM with integrated high speed point to point links |
May. 12, 2009 |
| 7533235 |
Reserve stacking |
May. 12, 2009 |
| 7533213 |
Memory hub and method for memory system performance monitoring |
May. 12, 2009 |
| 7529951 |
Memory subsystem voltage control and method that reprograms a preferred operating voltage |
May. 5, 2009 |
| 7529896 |
Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules |
May. 5, 2009 |
| 7526597 |
Buffered memory having a control bus and dedicated data lines |
Apr. 28, 2009 |
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