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Class Information
Number: 710/9
Name: Electrical computers and digital data processing systems: input/output > Input/output data processing > Peripheral configuration > Address assignment
Description: Subject matter further comprising means or steps for giving an identifier (i.e., address data) to the peripheral.


Patents under this class:
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Patent Number Title Of Patent Date Issued
5819115 Driver bundle including a compressed, self-extracting, executable driver for the host processor and an adapter driver for the processor of a network adapter card Oct. 6, 1998
5812821 Small computer system interface ("SCSI") controller Sep. 22, 1998
5809330 Conflict free PC in which only the I/O address of internal device is change when it is determined that the I/O address is overlap by expansion device Sep. 15, 1998
5808569 Transmission system implementing different coding principles Sep. 15, 1998
5805902 Structure and method for issuing interrupt requests as addresses and for decoding the addresses issued as interrupt requests Sep. 8, 1998
5802389 Expansion module address method and apparatus for a programmable logic controller Sep. 1, 1998
5802312 System for transmitting data files between computers in a wireless environment utilizing a file transfer agent executing on host system Sep. 1, 1998
5799203 System for receiving peripheral device capability information and selectively disabling corresponding processing unit function when the device failing to support such function Aug. 25, 1998
5797032 Bus for connecting extension cards to a data processing system and test method Aug. 18, 1998
5796988 Method and system using dedicated location to share information between real mode and protected mode drivers Aug. 18, 1998
5797036 Apparatus which prepares a master map portraying location of devices relative to bus interface circuits and copying the pertinent portion of the master map to each bus interface circuits Aug. 18, 1998
5794013 System and method for testing computer components in development environments Aug. 11, 1998
5790888 State machine for selectively performing an operation on a single or a plurality of registers depending upon the register address specified in a packet Aug. 4, 1998
5787306 Automatic assignment of I/O addresses in a computer system Jul. 28, 1998
5784644 Carrier for connecting device using electrical display device for indicating SCSI ID and controller ID of the attached device on the carriers facial assembly Jul. 21, 1998
5781796 System for automatic configuration of I/O base address without configuration program using readout data on common bus by responding device Jul. 14, 1998
5778196 Method and device for identifying a bus memory region Jul. 7, 1998
5768618 Method for performing sequence of actions in device connected to computer in response to specified values being written into snooped sub portions of address space Jun. 16, 1998
5757657 Adaptive incremental placement of circuits on VLSI chip May. 26, 1998
5748982 Apparatus for selecting a user programmable address for an I/O device May. 5, 1998
5745786 Method and apparatus for assigning memory space addresses to memory on computer interface boards Apr. 28, 1998
5740379 Method for generating unique addresses for electrical devices from input bit patterns being verifiable for admissibility Apr. 14, 1998
5740464 Architecture for providing input/output operations in a computer system Apr. 14, 1998
5727184 Method and apparatus for interfacing between peripherals of multiple formats and a single system bus Mar. 10, 1998
5727169 Electronically configurable connection device Mar. 10, 1998
5727152 Interface arrangement, and telecommunication system, and method Mar. 10, 1998
5724529 Computer system with multiple PC card controllers and a method of controlling I/O transfers in the system Mar. 3, 1998
5721840 Information processing apparatus incorporating automatic SCSI ID generation Feb. 24, 1998
5708831 Method of bus address assignment Jan. 13, 1998
5692161 Method and apparatus for operating a microcomputer in an emulation mode to access an external peripheral Nov. 25, 1997
5687388 Scalable tree structured high speed input/output subsystem architecture Nov. 11, 1997
5678056 Method and apparatus for control of serial communication by changing address conditions during and after communication start up Oct. 14, 1997
5675831 Method for automatic installation of a modem wherein unique identification for the device registry is computed from modem responses to queries by the system Oct. 7, 1997
5675830 Addressing scheme for control network having remote address request device Oct. 7, 1997
5666556 Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit Sep. 9, 1997
5664221 System for reconfiguring addresses of SCSI devices via a device address bus independent of the SCSI bus Sep. 2, 1997
5655149 System for identifying a primary processor and non-primary processors after system reboot independent of processor positions and without using default primary processor identification Aug. 5, 1997
5655148 Method for automatically configuring devices including a network adapter without manual intervention and without prior configuration information Aug. 5, 1997
5652845 Display apparatus Jul. 29, 1997
5644712 Indirect addressing of channels via logical channel groups Jul. 1, 1997
5642488 Method and apparatus for a host computer to stage a plurality of terminal addresses Jun. 24, 1997
5640594 Method and system for assigning peripheral device addresses Jun. 17, 1997
5640591 Method and apparatus for naming input/output devices in a computer system Jun. 17, 1997
5636342 Systems and method for assigning unique addresses to agents on a system management bus Jun. 3, 1997
5634074 Serial I/O device identifies itself to a computer through a serial interface during power on reset then it is being configured by the computer May. 27, 1997
5634075 Backward compatibility for plug and play systems May. 27, 1997
5628027 Method of determining the configuration of devices installed on a computer bus May. 6, 1997
5625847 High-speed ISA bus control system for changing command cycle execution speed by selectively using ISA bus controller and high-speed bus controller Apr. 29, 1997
5623692 Architecture for providing input/output operations in a computer system Apr. 22, 1997
5619724 System for assigning a unique identifier to components by storing a bit sequence from a selected bit line after detecting a predetermined sequence of data Apr. 8, 1997

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