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Class Information
Number: 710/66
Name: Electrical computers and digital data processing systems: input/output > Input/output data processing > Peripheral adapting > Input/output data modification > Width conversion
Description: Subject matter further comprising means or steps for transferring data between a peripheral that processes data of a first size and digital data processing system or computer that process data of a second size, different from the first.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7624211 |
Method for bus width negotiation of data storage devices |
Nov. 24, 2009 |
| 7620756 |
Method and apparatus for updating wide storage array over a narrow bus |
Nov. 17, 2009 |
| 7587535 |
Data transfer control device including endian conversion circuit with data realignment |
Sep. 8, 2009 |
| 7584314 |
Universal serial-to-parallel and parallel-to-serial cable interface and method |
Sep. 1, 2009 |
| 7574541 |
FIFO sub-system with in-line correction |
Aug. 11, 2009 |
| 7558892 |
Processing device peripheral with integral network interface circuitry |
Jul. 7, 2009 |
| 7555574 |
Asymmetric data path media access controller |
Jun. 30, 2009 |
| 7543088 |
Various methods and apparatuses for width and burst conversion |
Jun. 2, 2009 |
| 7506328 |
Method and system for optimizing performance of an apparatus |
Mar. 17, 2009 |
| 7490181 |
Data reproducing apparatus for transforming external input signal and method thereof |
Feb. 10, 2009 |
| 7480756 |
Electronic data processing circuit that transmits packed words via a bus |
Jan. 20, 2009 |
| 7472250 |
Storage control device, and control method for storage control device |
Dec. 30, 2008 |
| 7457904 |
Methods and systems for a reference clock |
Nov. 25, 2008 |
| 7447932 |
Semiconductor data processing device and data processing system |
Nov. 4, 2008 |
| 7433927 |
Network system, network control method, and signal sender/receiver |
Oct. 7, 2008 |
| 7433980 |
Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports |
Oct. 7, 2008 |
| 7421479 |
Network system, network control method, and signal sender/receiver |
Sep. 2, 2008 |
| 7418530 |
Storage device and method for controlling storage device packet size |
Aug. 26, 2008 |
| 7409479 |
Semiconductor integrated circuit |
Aug. 5, 2008 |
| 7376767 |
Distributed buffering system having programmable interconnecting logic and applications thereof |
May. 20, 2008 |
| 7376777 |
Performing an N-bit write access to an M.times.N-bit-only peripheral |
May. 20, 2008 |
| 7376780 |
Protocol converter to access AHB slave devices using the MDIO protocol |
May. 20, 2008 |
| 7350001 |
Method and apparatus for automatic word length conversion |
Mar. 25, 2008 |
| 7328299 |
Interface for compressed data transfer between host system and parallel data processing system |
Feb. 5, 2008 |
| 7319702 |
Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments |
Jan. 15, 2008 |
| 7308514 |
Configuring a communication link interface |
Dec. 11, 2007 |
| 7308536 |
System bus read data transfers with data ordering control bits |
Dec. 11, 2007 |
| 7293123 |
Asymmetric data path media access controller |
Nov. 6, 2007 |
| 7286067 |
Appliance with communication protocol emulation |
Oct. 23, 2007 |
| 7280051 |
Transmission and reception of a decomposed digitized signal |
Oct. 9, 2007 |
| 7281066 |
Memory access system including support for multiple bus widths |
Oct. 9, 2007 |
| 7243172 |
Fragment storage for data alignment and merger |
Jul. 10, 2007 |
| 7216185 |
Buffering apparatus and buffering method |
May. 8, 2007 |
| 7210008 |
Memory controller for padding and stripping data in response to read and write commands |
Apr. 24, 2007 |
| 7206876 |
Input/output interface of an integrated circuit device |
Apr. 17, 2007 |
| 7200697 |
High speed data transfer between mainframe storage systems |
Apr. 3, 2007 |
| 7197625 |
Alignment and ordering of vector elements for single instruction multiple data processing |
Mar. 27, 2007 |
| 7174398 |
Method and apparatus for implementing data mapping with shuffle algorithm |
Feb. 6, 2007 |
| 7171496 |
Data bus width conversion apparatus and data processing apparatus |
Jan. 30, 2007 |
| 7152131 |
Data processor having an access size control unit |
Dec. 19, 2006 |
| 7146566 |
Method and system for multiformat presentation |
Dec. 5, 2006 |
| 7130952 |
Data transmit method and data transmit apparatus |
Oct. 31, 2006 |
| 7103702 |
Memory device |
Sep. 5, 2006 |
| 7092439 |
Means and method of data encoding and communication at rates above the channel bandwidth |
Aug. 15, 2006 |
| 7076590 |
Asic expansion module for PDA |
Jul. 11, 2006 |
| 7072997 |
Asymmetric data path media access controller |
Jul. 4, 2006 |
| 7058736 |
Reordering of burst data transfers across a host bridge |
Jun. 6, 2006 |
| 7058745 |
Data terminal equipment |
Jun. 6, 2006 |
| 7051126 |
Hardware accelerated compression |
May. 23, 2006 |
| 7047332 |
Data transfer control device and electronic instrument |
May. 16, 2006 |
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