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Class Information
Number: 710/49
Name: Electrical computers and digital data processing systems: input/output > Input/output data processing > Input/output access regulation > Input/output interrupting > Masking
Description: Subject matter further comprising means or steps for inhibiting the servicing of the access requests.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7587544 |
Extending secure digital input output capability on a controller bus |
Sep. 8, 2009 |
| 7584310 |
Signal processing device |
Sep. 1, 2009 |
| 7505460 |
Address validating data structure used for validating addresses |
Mar. 17, 2009 |
| 7426728 |
Reducing latency, when accessing task priority levels |
Sep. 16, 2008 |
| 7296097 |
Memory card and initialization setting method thereof to avoid initializing operation failure in a memory card |
Nov. 13, 2007 |
| 7287103 |
Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes |
Oct. 23, 2007 |
| 7188203 |
Method and apparatus for dynamic suppression of spurious interrupts |
Mar. 6, 2007 |
| 6963934 |
Hibernation of computer systems |
Nov. 8, 2005 |
| 6944739 |
Register bank |
Sep. 13, 2005 |
| 6922764 |
Memory, processor system and method for performing write operations on a memory region |
Jul. 26, 2005 |
| 6910105 |
Associative memory having a mask function for use in a network router |
Jun. 21, 2005 |
| 6883037 |
Fast data decoder that operates with reduced output buffer bounds checking |
Apr. 19, 2005 |
| 6865644 |
System and method for industrial controller with an I/O processor using cache memory to optimize exchange of shared data |
Mar. 8, 2005 |
| 6845409 |
Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices |
Jan. 18, 2005 |
| 6839857 |
Interrupt controller in an interface device or information processing system |
Jan. 4, 2005 |
| 6823402 |
Apparatus and method for distribution of signals from a high level data link controller to multiple digital signal processor cores |
Nov. 23, 2004 |
| 6816933 |
Serial device daisy chaining method and apparatus |
Nov. 9, 2004 |
| 6816916 |
Data storage system having multi-cast/unicast |
Nov. 9, 2004 |
| 6813689 |
Communications architecture for a high throughput storage processor employing extensive I/O parallelization |
Nov. 2, 2004 |
| 6742060 |
Look-up table based circuitry for sharing an interrupt between disk drive interfaces |
May. 25, 2004 |
| 6643748 |
Programmatic masking of storage units |
Nov. 4, 2003 |
| 6629180 |
Method of performing a task in real time by a digital signal processor |
Sep. 30, 2003 |
| 6574693 |
Method and apparatus for gating interrupts in a computing system |
Jun. 3, 2003 |
| 6574294 |
Data streaming for non-DMA digital computing devices |
Jun. 3, 2003 |
| 6574702 |
Method and apparatus for determining an exact match in a content addressable memory device |
Jun. 3, 2003 |
| 6564317 |
Method and apparatus for securing computer firmware wherein unlocking of nonvolatile memory is prohibited unless address line masking Is disabled during an initialization event |
May. 13, 2003 |
| 6539455 |
Method and apparatus for determining an exact match in a ternary content addressable memory device |
Mar. 25, 2003 |
| 6523108 |
Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string |
Feb. 18, 2003 |
| 6499081 |
Method and apparatus for determining a longest prefix match in a segmented content addressable memory device |
Dec. 24, 2002 |
| 6484255 |
Selective writing of data elements from packed data based upon a mask using predication |
Nov. 19, 2002 |
| 6473853 |
Method and apparatus for initializing a computer system that includes disabling the masking of a maskable address line |
Oct. 29, 2002 |
| 6446189 |
Computer system including a novel address translation mechanism |
Sep. 3, 2002 |
| 6317803 |
High-throughput interconnect having pipelined and non-pipelined bus transaction modes |
Nov. 13, 2001 |
| 6263395 |
System and method for serial interrupt scanning |
Jul. 17, 2001 |
| 6243786 |
Apparatus and method for generating an interrupt prohibited zone in pipelined data processors |
Jun. 5, 2001 |
| 6222846 |
Method and system for employing a non-masking interrupt as an input-output processor interrupt |
Apr. 24, 2001 |
| 6216218 |
Processor having a datapath and control logic constituted with basis execution blocks |
Apr. 10, 2001 |
| 6167470 |
SCSI system capable of connecting maximum number of high speed SCSI devices with maintaining positive operation |
Dec. 26, 2000 |
| 6167472 |
System for communicating with and initializing a computer peripheral utilizing a masked value generated by exclusive-or of data and corresponding mask |
Dec. 26, 2000 |
| 6125418 |
Method and apparatus for enabling a computer user to convert a computer system to an intelligent I/O system |
Sep. 26, 2000 |
| 6115779 |
Interrupt management system having batch mechanism for handling interrupt events |
Sep. 5, 2000 |
| 6088791 |
Computer processor system for implementing the ESA/390 STOSM and STNSM instructions without serialization or artificially extending processor execution time |
Jul. 11, 2000 |
| 6055587 |
Integrated circuit SCSI I/O cell having signal assertion edge triggered timed glitch filter that defines a strobe masking period to protect the contents of data latches |
Apr. 25, 2000 |
| 6003109 |
Method and apparatus for processing interrupts in a data processing system |
Dec. 14, 1999 |
| 5983025 |
Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses |
Nov. 9, 1999 |
| 5983314 |
Output buffer having inherently precise data masking |
Nov. 9, 1999 |
| 5974481 |
Method for estimating the probability of collisions of fingerprints |
Oct. 26, 1999 |
| 5964853 |
Interface controller including hardware mechanism to handle PS/2 interface |
Oct. 12, 1999 |
| 5935220 |
Apparatus and method for high speed data and command transfer over an interface |
Aug. 10, 1999 |
| 5905913 |
System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor |
May. 18, 1999 |
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