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Class Information
Number: 710/40
Name: Electrical computers and digital data processing systems: input/output > Input/output data processing > Input/output access regulation > Access prioritization
Description: Subject matter further comprising means or steps for preferring certain of the peripherals, or digital data processing systems or computers over others in servicing requests therefrom to transfer data.










Sub-classes under this class:

Class Number Class Name Patents
710/41 Dynamic 149
710/42 Group 65
710/43 Physical position 59
710/44 Prioritized polling 68
710/45 Time-slot accessing 143


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
6484217 Managing shared devices in a data processing system Nov. 19, 2002
6473809 Scheduling method and apparatus for network-attached storage devices and other systems Oct. 29, 2002
6466996 Method and system for implementing intelligent distributed input-output processing as a software process in a host operating system environment Oct. 15, 2002
6442658 Method and apparatus for improving playback of interactive multimedia works Aug. 27, 2002
6442631 Allocating system resources based upon priority Aug. 27, 2002
6442635 Processor architecture for virtualizing selective external bus transactions Aug. 27, 2002
6434631 Method and system for providing computer storage access with quality of service guarantees Aug. 13, 2002
6430642 Methods and apparatus for prioritization of access to external devices Aug. 6, 2002
6401145 Method of transferring data using an interface element and a queued direct input-output device Jun. 4, 2002
6393505 Methods and apparatus for data bus arbitration May. 21, 2002
6378036 Queuing architecture including a plurality of queues and associated method for scheduling disk access requests for video content Apr. 23, 2002
6363441 TIMING CONTROLLER HAVING DEPENDENCY MEMORY, SELECTION SERIALIZATION COMPONENT AND REORDERING COMPONENT FOR MAINTAINING TIME DEPENDENCIES IN CONVERSIONS BETWEEN SEQUENTIAL AND PARALLEL OPERATIO Mar. 26, 2002
6363445 Method of bus arbitration using requesting device bandwidth and priority ranking Mar. 26, 2002
6351783 Method and apparatus for isochronous data transport over an asynchronous bus Feb. 26, 2002
6345324 Apparatus for transferring data using an interface element and a queued direct input-output device Feb. 5, 2002
6345325 Method and apparatus for ensuring accurate and timely processing of data using a queued direct input-output device Feb. 5, 2002
6345326 Computer program device and product for timely processing of data using a queued direct input-output device Feb. 5, 2002
6330647 Memory bandwidth allocation based on access count priority scheme Dec. 11, 2001
6324616 Dynamically inhibiting competing resource requesters in favor of above threshold usage requester to reduce response delay Nov. 27, 2001
6321279 System for implementing intelligent I/O processing in a multi-processor system by redirecting I/O messages to a target central processor selected from the multi-processor system Nov. 20, 2001
6321309 Memory arbitration scheme with circular sequence register Nov. 20, 2001
6317800 System for reducing arbitrated-loop overhead by maintaining control of a communications channel as long as a predetermined amount of data is available within control of channel node Nov. 13, 2001
6314485 Automatic status register Nov. 6, 2001
6304923 Method for prioritizing data transfer request by comparing a latency identifier value received from an I/O device with a predetermined range of values Oct. 16, 2001
6301627 Method/system for identifying delayed predetermined information transfer request as bypassable by subsequently-generated information transfer request using bypass enable bit in bridge translat Oct. 9, 2001
6298409 System for data and interrupt posting for computer devices Oct. 2, 2001
6295553 Method and apparatus for prioritizing delivery of data transfer requests Sep. 25, 2001
6279054 Arbitrator for multiple processes sharing a port Aug. 21, 2001
6275890 Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration Aug. 14, 2001
6269413 System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO sel Jul. 31, 2001
6260090 Circuit arrangement and method incorporating data buffer with priority-based data storage Jul. 10, 2001
6260081 Direct memory access engine for supporting multiple virtual direct memory access channels Jul. 10, 2001
6256698 Method of and apparatus for providing self-sustained even arbitration within an IEEE 1394 serial bus network of devices Jul. 3, 2001
6253260 Input/output data access request with assigned priority handling Jun. 26, 2001
6253262 Arbitrating FIFO implementation which positions input request in a buffer according to its status Jun. 26, 2001
6253263 System with logic gates having a progressive number of inputs connected to a first connection matrix receiving signals to be arbitrated from peripheral devices Jun. 26, 2001
6249846 Distributed data dependency stall mechanism Jun. 19, 2001
6223244 Method for assuring device access to a bus having a fixed priority arbitration scheme Apr. 24, 2001
6223243 Access control method with plural users having I/O commands prioritized in queues corresponding to plural memory units Apr. 24, 2001
6216178 Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution Apr. 10, 2001
6199124 Arbitration system based on requester class and relative priority including transmit descriptor valid bit for a shared resource having multiple requesters Mar. 6, 2001
6199123 Computer system for supporting increased PCI master devices without the requiring additional bridge chips Mar. 6, 2001
6199118 System and method for aligning an initial cache line of data read from an input/output device by a central processing unit Mar. 6, 2001
6195724 Methods and apparatus for prioritization of access to external devices Feb. 27, 2001
6192428 Method/apparatus for dynamically changing FIFO draining priority through asynchronous or isochronous DMA engines in response to packet type and predetermined high watermark being reached Feb. 20, 2001
6182120 Method and system for scheduling queued messages based on queue delay and queue priority Jan. 30, 2001
6175930 Demand based sync bus operation Jan. 16, 2001
6163827 Method and apparatus for round-robin flash channel arbitration Dec. 19, 2000
6160812 Method and apparatus for supplying requests to a scheduler in an input buffered multiport switch Dec. 12, 2000
6157963 System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients Dec. 5, 2000

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