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Class Information
Number: 710/40
Name: Electrical computers and digital data processing systems: input/output > Input/output data processing > Input/output access regulation > Access prioritization
Description: Subject matter further comprising means or steps for preferring certain of the peripherals, or digital data processing systems or computers over others in servicing requests therefrom to transfer data.

Sub-classes under this class:

Class Number Class Name Patents
710/41 Dynamic 149
710/42 Group 65
710/43 Physical position 59
710/44 Prioritized polling 68
710/45 Time-slot accessing 143

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
6917990 Method and structure for read prefetch in a storage complex architecture Jul. 12, 2005
6915396 Fast priority determination circuit with rotating priority Jul. 5, 2005
6915360 Cell buffering system with priority cache in an ATM system Jul. 5, 2005
6915359 Data transfer device, data transfer method, data transfer program and computer readable storage medium thereof Jul. 5, 2005
6904474 Using write request queue to prevent bottlenecking on slow ports in transfer controller with hub and ports architecture Jun. 7, 2005
6901487 Device for processing data by means of a plurality of processors May. 31, 2005
6898678 Shared memory with programmable size May. 24, 2005
6898679 Method and apparatus for reordering memory requests for page coherency May. 24, 2005
6892250 Command queue processor May. 10, 2005
6883045 Apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system Apr. 19, 2005
6877072 Real-time shared disk system for computer clusters Apr. 5, 2005
6877056 System with arbitration scheme supporting virtual address networks and having split ownership and access right coherence mechanism Apr. 5, 2005
6865635 Access scheme for a collective resource using a plurality of states Mar. 8, 2005
6859845 System for resolving conflicts due to simultaneous media streams and method thereof Feb. 22, 2005
6851059 Method and system for choosing a queue protection key that is tamper-proof from an application Feb. 1, 2005
6851011 Reordering hardware for mass storage command queue Feb. 1, 2005
6848012 Method and system for an adaptive multimode media queue Jan. 25, 2005
6842861 Method and system for detecting viruses on handheld computers Jan. 11, 2005
6842827 Cache coherency arrangement to enhance inbound bandwidth Jan. 11, 2005
6842830 Mechanism for handling explicit writeback in a cache coherent multi-node architecture Jan. 11, 2005
6839797 Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem Jan. 4, 2005
6839817 Priority management of a disk array Jan. 4, 2005
6834314 Method and apparatus for reordering packet transactions within a peripheral interface circuit Dec. 21, 2004
6826630 Prioritizing commands in a data storage device Nov. 30, 2004
6820151 Starvation avoidance mechanism for an I/O node of a computer system Nov. 16, 2004
6816923 Arbitrating and servicing polychronous data requests in direct memory access Nov. 9, 2004
6816926 Storage system Nov. 9, 2004
6810434 Multimedia interface having a processor and reconfigurable logic Oct. 26, 2004
6807588 Method and apparatus for maintaining order in a queue by combining entry weights and queue weights Oct. 19, 2004
6807586 Increased computer peripheral throughput by using data available withholding Oct. 19, 2004
6804758 Method for adaptive arbitration of requests for memory access in a multi-stage pipeline engine Oct. 12, 2004
6802064 Data transfer request processing scheme for reducing mechanical actions in data storage system Oct. 5, 2004
6799228 Input/output control apparatus, input/output control method and information storage system Sep. 28, 2004
6795878 Verifying cumulative ordering of memory instructions Sep. 21, 2004
6782435 Device for spatially and temporally reordering for data between a processor, memory and peripherals Aug. 24, 2004
6779047 Serial communication port arbitration between a hotsync manager and a wireless connection manager Aug. 17, 2004
6779061 Method and apparatus implementing a FIFO with discrete blocks Aug. 17, 2004
6763404 System and method for scheduling of random commands to minimize impact of locational uncertainty Jul. 13, 2004
6763469 Systems for local network security Jul. 13, 2004
6763402 Data storage subsystem Jul. 13, 2004
6760791 Buffer circuit for a peripheral interface circuit in an I/O node of a computer system Jul. 6, 2004
6760792 Buffer circuit for rotating outstanding transactions Jul. 6, 2004
6757754 Data transfer unit for receiving general purpose commands when no expedited command is arriving Jun. 29, 2004
6745262 Method, system, program, and data structure for queuing requests having different priorities Jun. 1, 2004
6742075 Arrangement for instigating work in a channel adapter based on received address information and stored context information May. 25, 2004
6742063 Method and apparatus for efficient transfer of data packets May. 25, 2004
6735639 Direct memory access transfer control circuit May. 11, 2004
6732198 Methods and apparatus for saving and restoring scatter/gather list processing context in intelligent controllers May. 4, 2004
6732196 Allowing slots belonging to a second slot category to receive I/O access requests belonging to a first and a second access request categories in a round robin fashion May. 4, 2004
6728790 Tagging and arbitration mechanism in an input/output node of a computer system Apr. 27, 2004

1 2 3 4 5 6 7 8 9 10 11

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