| |
 |
|
Class Information
Number: 710/310
Name: Electrical computers and digital data processing systems: input/output > Intrasystem connection (e.g., bus and bus transaction processing) > Bus interface architecture > Bus bridge > Buffer or que control
Description: Subject matter including specific means or steps for control of temporary storage of data being transferred between coupled buses
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617343 |
Scalable bus structure |
Nov. 10, 2009 |
| 7613859 |
Back-off timing mechanism in a digital signal processor |
Nov. 3, 2009 |
| 7610061 |
Communication device and method having a common platform |
Oct. 27, 2009 |
| 7603511 |
Cyclic buffer mechanism for receiving wireless data under varying data traffic conditions |
Oct. 13, 2009 |
| 7603487 |
Hardware configurable hub interface unit |
Oct. 13, 2009 |
| 7603508 |
Scalable distributed memory and I/O multiprocessor systems and associated methods |
Oct. 13, 2009 |
| 7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation |
Oct. 13, 2009 |
| 7594057 |
Method and system for processing DMA requests |
Sep. 22, 2009 |
| 7594047 |
Buffer circuit |
Sep. 22, 2009 |
| 7590764 |
System and method for dynamic buffer allocation |
Sep. 15, 2009 |
| 7590789 |
Optimizing clock crossing and data path latency |
Sep. 15, 2009 |
| 7574539 |
Dynamic A-MSDU enabling |
Aug. 11, 2009 |
| 7574544 |
Flow control by supplying a remote start bit onto a single-wire bus |
Aug. 11, 2009 |
| 7570534 |
Enqueue event first-in, first-out buffer (FIFO) |
Aug. 4, 2009 |
| 7571271 |
Lane merging |
Aug. 4, 2009 |
| 7568118 |
Deterministic operation of an input/output interface |
Jul. 28, 2009 |
| 7562165 |
USB host system, AV data reproduction apparatus and AV data recording apparatus |
Jul. 14, 2009 |
| 7558901 |
Apparatus and method for connecting processor to bus |
Jul. 7, 2009 |
| 7558895 |
Interconnect logic for a data processing apparatus |
Jul. 7, 2009 |
| 7551626 |
Queueing system for processors in packet routing operations |
Jun. 23, 2009 |
| 7539791 |
Method and apparatus for optimizing data buffering |
May. 26, 2009 |
| 7539810 |
System, method and storage medium for a multi-mode memory buffer device |
May. 26, 2009 |
| 7536495 |
Certified memory-to-memory data transfer between active-active raid controllers |
May. 19, 2009 |
| 7536494 |
Expandable slave device system with buffered subsystems |
May. 19, 2009 |
| 7533216 |
Device and method for simulating a hard disk |
May. 12, 2009 |
| 7529867 |
Adaptive, scalable I/O request handling architecture in virtualized computer systems and networks |
May. 5, 2009 |
| 7529876 |
Tag allocation method |
May. 5, 2009 |
| 7526594 |
USB data transfer method |
Apr. 28, 2009 |
| 7526593 |
Packet combiner for a packetized bus with dynamic holdoff time |
Apr. 28, 2009 |
| 7519759 |
Pipeline synchronisation device |
Apr. 14, 2009 |
| 7514289 |
Methods and structures for facilitating proximity communication |
Apr. 7, 2009 |
| 7516262 |
Data transfer apparatus with control of buses to enable reading of predetermined data sizes |
Apr. 7, 2009 |
| 7500045 |
Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system |
Mar. 3, 2009 |
| 7500044 |
Digital phase relationship lock loop |
Mar. 3, 2009 |
| 7496698 |
System and method for efficient implementation of a shared receive queue |
Feb. 24, 2009 |
| 7496707 |
Dynamically scalable queues for performance driven PCI express memory traffic |
Feb. 24, 2009 |
| 7493446 |
System and method for completing full updates to entire cache lines stores with address-only bus operations |
Feb. 17, 2009 |
| 7487284 |
Transaction flow and ordering for a packet processing engine, located within an input-output hub |
Feb. 3, 2009 |
| 7484031 |
Bus connection device |
Jan. 27, 2009 |
| 7484030 |
Storage controller and methods for using the same |
Jan. 27, 2009 |
| 7484029 |
Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters |
Jan. 27, 2009 |
| 7484028 |
Burst-capable bus bridges for coupling devices to interface buses |
Jan. 27, 2009 |
| 7478189 |
Deadlock avoidance in a bus fabric |
Jan. 13, 2009 |
| 7454551 |
Reconstructing transaction order using clump tags |
Nov. 18, 2008 |
| 7450678 |
Asynchronous signal input apparatus and sampling frequency conversion apparatus |
Nov. 11, 2008 |
| 7447826 |
Receive buffer in a data storage system |
Nov. 4, 2008 |
| 7444444 |
Message processing system and method using external storage |
Oct. 28, 2008 |
| 7441065 |
Method and apparatus for a two-wire serial command bus interface |
Oct. 21, 2008 |
| 7424567 |
Method, system, and apparatus for a dynamic retry buffer that holds a packet for transmission |
Sep. 9, 2008 |
| 7424566 |
Method, system, and apparatus for dynamic buffer space allocation |
Sep. 9, 2008 |
|
|
|
