| |
 |
|
Class Information
Number: 710/115
Name: Electrical computers and digital data processing systems: input/output > Intrasystem connection (e.g., bus and bus transaction processing) > Bus access regulation > Centralized bus arbitration > Static bus prioritization > Physical position bus prioritization
Description: Subject matter including means or steps for granting the contending digital data processing system components access to the shared bus based on their physical location on the bus.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7315909 |
Hierarchized arbitration method |
Jan. 1, 2008 |
| 7051132 |
Bus system and path decision method therefor |
May. 23, 2006 |
| 6976108 |
System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities |
Dec. 13, 2005 |
| 6928501 |
Serial device daisy chaining method and apparatus |
Aug. 9, 2005 |
| 6901487 |
Device for processing data by means of a plurality of processors |
May. 31, 2005 |
| 6898766 |
Simplifying integrated circuits with a common communications bus |
May. 24, 2005 |
| 6862639 |
Computer system including a receiver interface circuit with a scatter pointer queue and related methods |
Mar. 1, 2005 |
| 6651110 |
Configurable object for industrial control and monitoring networks |
Nov. 18, 2003 |
| 6502149 |
Plural bus data storage system |
Dec. 31, 2002 |
| 6397281 |
Bus arbitration system |
May. 28, 2002 |
| 6339807 |
Multiprocessor system and the bus arbitrating method of the same |
Jan. 15, 2002 |
| 6286070 |
Shared memory access device and method |
Sep. 4, 2001 |
| 6185647 |
Dynamic bus control apparatus for optimized device connection |
Feb. 6, 2001 |
| 6018781 |
Work station having simultaneous access to registers contained in two different interfaces |
Jan. 25, 2000 |
| 5950229 |
System for accelerating memory bandwidth |
Sep. 7, 1999 |
| 5931931 |
Method for bus arbitration in a multiprocessor system |
Aug. 3, 1999 |
| 5715475 |
Topological identification and initialization of a system for processing video information |
Feb. 3, 1998 |
| 5210846 |
One-wire bus architecture |
May. 11, 1993 |
| RE33705 |
Interchangeable interface circuit structure |
Oct. 1, 1991 |
| 4959775 |
Bus regulating system |
Sep. 25, 1990 |
| 4670855 |
Interchangeable interface circuit structure |
Jun. 2, 1987 |
|
|
|
