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Class Information
Number: 710/110
Name: Electrical computers and digital data processing systems: input/output > Intrasystem connection (e.g., bus and bus transaction processing) > Bus access regulation > Bus master/slave controlling
Description: Subject matter wherein a digital data processing system component is provided with control over other digital data processing system components connected to the bus.

Patents under this class:
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Patent Number Title Of Patent Date Issued
5764935 High speed active bus Jun. 9, 1998
5765217 Method and apparatus to perform bus reflection operation using a data processor Jun. 9, 1998
5761451 Configuration with several active and passive bus users Jun. 2, 1998
5761697 Identifiable modules on a serial bus system and corresponding identification methods Jun. 2, 1998
5758098 Method and apparatus for providing a high throughput two-conductor serial interface with support for slave device detection May. 26, 1998
5754799 System and method for bus contention resolution May. 19, 1998
5748468 Prioritized co-processor resource manager and method May. 5, 1998
5745698 System and method for communicating between devices Apr. 28, 1998
5745707 Bus control device for computer system having computer and DMA device Apr. 28, 1998
5737545 Computer bus mastery system and method having a lock mechanism Apr. 7, 1998
5737546 System bus with separate address and data bus protocols Apr. 7, 1998
5734830 Multi-equipment routing method and master station for layered protocol communication network system Mar. 31, 1998
5729686 Method for initializing a network having a plurality of network subscribers capable of acting as masters Mar. 17, 1998
5729701 Method and arrangement to control a data network Mar. 17, 1998
5727172 Method and apparatus for performing atomic accesses in a data processing system Mar. 10, 1998
5721737 Serial transmission system for controlling a network of I/O devices Feb. 24, 1998
5721882 Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus Feb. 24, 1998
5721946 Signal transfer method having unique word assigned to terminal stations appended before control frames originated from control station and terminal stations Feb. 24, 1998
5717873 Deadlock avoidance mechanism and method for multiple bus topology Feb. 10, 1998
5717931 Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous Feb. 10, 1998
5715407 Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packets Feb. 3, 1998
5715475 Topological identification and initialization of a system for processing video information Feb. 3, 1998
5708794 Multi-purpose usage of transaction backoff and bus architecture supporting same Jan. 13, 1998
5701502 Isolating a central processing unit from the operating system controlling said unit and its associated hardware for interaction of the unit with data handling apparatus alien to the operating Dec. 23, 1997
5699516 Method and apparatus for implementing a in-order termination bus protocol within a data processing system Dec. 16, 1997
5689631 Parallel processing computer and method of solving a problem using simultaneously executed different and competing procedures Nov. 18, 1997
5682485 Deadlock avoidance for switched interconnect bus systems Oct. 28, 1997
5680643 Data bus including address request line for allowing request for a subsequent address word during a burst mode transfer Oct. 21, 1997
5659707 Transfer labeling mechanism for multiple outstanding read requests on a split transaction bus Aug. 19, 1997
5655131 SIMD architecture for connection to host processor's bus Aug. 5, 1997
5649209 Bus coupling information processing system for multiple access to system bus Jul. 15, 1997
5644174 Universal AC sequencer for a server Jul. 1, 1997
5640517 Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order Jun. 17, 1997
5640518 Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length Jun. 17, 1997
5634076 DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer May. 27, 1997
5630152 Communication protocol between master and slave device with register information sharing May. 13, 1997
5630153 Integrated digital signal processor/general purpose CPU with shared internal memory May. 13, 1997
5623610 System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset Apr. 22, 1997
5615404 System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochrono Mar. 25, 1997
5608879 Method and apparatus for arbitrating data requests and responses thereto as separate bus transactions Mar. 4, 1997
5604865 Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU Feb. 18, 1997
5604874 Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment Feb. 18, 1997
5596729 First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus Jan. 21, 1997
5590286 Method and apparatus for the pipelining of data during direct memory accesses Dec. 31, 1996
5590369 Bus supporting a plurality of data transfer sizes and protocols Dec. 31, 1996
5588123 Bus system Dec. 24, 1996
5586297 Partial cache line write transactions in a computing system with a write back cache Dec. 17, 1996
5586299 Systems and methods for accessing multi-port memories Dec. 17, 1996
5581716 IDE type CD-ROM drive interfacing circuit Dec. 3, 1996
5579492 Data processing system and a method for dynamically ignoring bus transfer termination control signals for a predetermined amount of time Nov. 26, 1996

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