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Class Information
Number: 710/110
Name: Electrical computers and digital data processing systems: input/output > Intrasystem connection (e.g., bus and bus transaction processing) > Bus access regulation > Bus master/slave controlling
Description: Subject matter wherein a digital data processing system component is provided with control over other digital data processing system components connected to the bus.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6070205 High-speed processor system having bus arbitration mechanism May. 30, 2000
6055577 System for granting bandwidth for real time processes and assigning bandwidth for non-real time processes while being forced to periodically re-arbitrate for new assigned bandwidth Apr. 25, 2000
6047345 Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment Apr. 4, 2000
6032178 Method and arrangement for data transmission between units on a bus system selectively transmitting data in one of a first and a second data transmission configurations Feb. 29, 2000
6029218 Data transfer method and data transfer device Feb. 22, 2000
6012004 System and method for managing time for vehicle fault diagnostic apparatus Jan. 4, 2000
6006020 Video peripheral circuitry exercising bus master control over a bus of a host computer Dec. 21, 1999
6000043 Method and apparatus for management of peripheral devices coupled to a bus Dec. 7, 1999
5996036 Bus transaction reordering in a computer system having unordered slaves Nov. 30, 1999
5983024 Method and apparatus for robust data broadcast on a peripheral component interconnect bus Nov. 9, 1999
5983300 Dynamic window mechanism for preventing invalid information propagation from the PCI bus Nov. 9, 1999
5978879 Bus bridge apparatus Nov. 2, 1999
5968150 Processor element having a plurality of CPUs for use in a multiple processor system Oct. 19, 1999
5968153 Mechanism for high bandwidth DMA transfers in a PCI environment Oct. 19, 1999
5964845 Processing system having improved bi-directional serial clock communication circuitry Oct. 12, 1999
5964856 Mechanism for data strobe pre-driving during master changeover on a parallel bus Oct. 12, 1999
5943483 Method and apparatus for controlling access to a bus in a data processing system Aug. 24, 1999
5931932 Dynamic retry mechanism to prevent corrupted data based on posted transactions on the PCI bus Aug. 3, 1999
5928345 Field instrument with data bus communications protocol Jul. 27, 1999
5928346 Method for enhanced peripheral component interconnect bus split data transfer Jul. 27, 1999
5930485 Deadlock avoidance in a computer system having unordered slaves Jul. 27, 1999
5925118 Methods and architectures for overlapped read and write operations Jul. 20, 1999
5920695 Method and means for bidirectional peer-coupled communication across a single ESCON interface Jul. 6, 1999
5920891 Architecture and method for controlling a cache memory Jul. 6, 1999
5907689 Master-target based arbitration priority May. 25, 1999
5889966 Data processor having bus controller for controlling a plurality of buses independently of each other Mar. 30, 1999
5887194 Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked Mar. 23, 1999
5878234 Low power serial protocol translator for use in multi-circuit board electronic systems Mar. 2, 1999
5864653 PCI hot spare capability for failed components Jan. 26, 1999
5862354 Universal asynchronous receiver/transmitter (UART) slave device containing an identifier for communication on a one-wire bus Jan. 19, 1999
5857081 Method and apparatus for controlling a master abort in a computer system Jan. 5, 1999
5854906 Method and apparatus for fast-forwarding slave request in a packet-switched computer system Dec. 29, 1998
5841988 Interprocessor communications data transfer and error detection in a multiprocessing environment Nov. 24, 1998
5835714 Method and apparatus for reservation of data buses between multiple storage control elements Nov. 10, 1998
5835785 Multiplexed three line synchronous/full-duplex asychronous data bus and method therefor Nov. 10, 1998
5828318 System and method for selecting a subset of autonomous and independent slave entities Oct. 27, 1998
5828852 Method for operation of a bus system for highly flexible and quick data transmission between units connected to the bus system and configuration for carrying out the method Oct. 27, 1998
5825784 Testing and diagnostic mechanism Oct. 20, 1998
5819051 Low speed serial bus protocol and circuitry Oct. 6, 1998
5805837 Method for optimizing reissue commands in master-slave processing systems Sep. 8, 1998
5797018 Apparatus and method of preventing a deadlock condition in a computer system Aug. 18, 1998
5793994 Synchronous event posting by a high throughput bus Aug. 11, 1998
5793996 Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer Aug. 11, 1998
5790811 System and method for performing data transfers during PCI idle clock cycles Aug. 4, 1998
5787263 Method of an apparatus for controlling data transfer Jul. 28, 1998
5787264 Method and apparatus for arbitrating access to a shared bus Jul. 28, 1998
5784581 Apparatus and method for operating a peripheral device as either a master device or a slave device Jul. 21, 1998
5774354 Programmable controller and exclusive control communicating method therefor Jun. 30, 1998
5774679 Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement Jun. 30, 1998
5774680 Interfacing direct memory access devices to a non-ISA bus Jun. 30, 1998

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