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Class Information
Number: 710/110
Name: Electrical computers and digital data processing systems: input/output > Intrasystem connection (e.g., bus and bus transaction processing) > Bus access regulation > Bus master/slave controlling
Description: Subject matter wherein a digital data processing system component is provided with control over other digital data processing system components connected to the bus.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6286057 Method and arrangement for allowing a computer to communicate with a data storage device Sep. 4, 2001
6282598 PCI bus system wherein target latency information are transmitted along with a retry request Aug. 28, 2001
6279063 Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller Aug. 21, 2001
6275887 Method and apparatus for terminating a bus transaction if the target is not ready Aug. 14, 2001
6272577 Data processing system with master and slave devices and asymmetric signal swing bus Aug. 7, 2001
6272578 Programmable controller Aug. 7, 2001
6260174 Method and apparatus for fast-forwarding slave requests in a packet-switched computer system Jul. 10, 2001
6256693 Master/slave data bus employing undirectional address and data lines and request/acknowledge signaling Jul. 3, 2001
6240477 Data bus device which requests additional information as well as apparatus information from devices attached to a data bush and which retains the additional information with the apparatus info May. 29, 2001
6240478 Apparatus and method for addressing electronic modules May. 29, 2001
6230224 Fan-out expansion circuit for RS-485 multidrop connection May. 8, 2001
6226700 Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices May. 1, 2001
6219735 Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement Apr. 17, 2001
6212588 Integrated circuit for controlling a remotely located mass storage peripheral device Apr. 3, 2001
6212620 Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals Apr. 3, 2001
6209022 Slave station with two output circuits commonly and directly connected to a line for serially transmitting data to a master station in two operational modes Mar. 27, 2001
6205501 Apparatus and method for handling universal serial bus control transfers Mar. 20, 2001
6199130 Concurrent maintenance for PCI based DASD subsystem with concurrent maintenance message being communicated between SPCN (system power control network) and I/O adapter using PCI bridge Mar. 6, 2001
6199133 Management communication bus for networking devices Mar. 6, 2001
6195724 Methods and apparatus for prioritization of access to external devices Feb. 27, 2001
6192281 Network accessible interface for a process control network Feb. 20, 2001
6189061 Multi-master bus system performing atomic transactions and method of operating same Feb. 13, 2001
6185651 SCSI bus extender utilizing tagged queuing in a multi-initiator environment Feb. 6, 2001
6178462 Protocol for using a PCI interface for connecting networks Jan. 23, 2001
6173349 Shared bus system with transaction and destination ID Jan. 9, 2001
6163826 Method and apparatus for non-concurrent arbitration of multiple busses Dec. 19, 2000
6157971 Source-destination re-timed cooperative communication bus Dec. 5, 2000
6151648 High speed bus system and method for using voltage and timing oscillating references for signal detection Nov. 21, 2000
6147682 Monitor for use with computer system and method of controlling supply of power to computer peripherals connected with the monitor Nov. 14, 2000
6145041 Remote multi-level control bus Nov. 7, 2000
6145044 PCI bus bridge with transaction forwarding controller for avoiding data transfer errors Nov. 7, 2000
6141736 Arrangement with master and slave units Oct. 31, 2000
6141713 Bus arbitrator with a hierarchical control structure Oct. 31, 2000
6141715 Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction Oct. 31, 2000
6125419 Bus system, printed circuit board, signal transmission line, series circuit and memory module Sep. 26, 2000
6122694 Serial bus controller Sep. 19, 2000
6119181 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures Sep. 12, 2000
6119189 Bus master transactions on a low pin count bus Sep. 12, 2000
6112270 Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system Aug. 29, 2000
6112272 Non-invasive bus master back-off circuit and method for systems having a plurality of bus masters Aug. 29, 2000
6104876 PCI bus master retry fixup Aug. 15, 2000
6105055 Method and apparatus for asynchronous multimedia collaboration Aug. 15, 2000
6105119 Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems Aug. 15, 2000
6092218 System and method for self-referential accesses in a multiprocessor computer Jul. 18, 2000
6088517 Interfacing direct memory access devices to a non-ISA bus Jul. 11, 2000
6088750 Method and system for arbitrating between bus masters having diverse bus acquisition protocols Jul. 11, 2000
6081859 Address dependent retry system to program the retry latency of an initiator PCI agent Jun. 27, 2000
6081860 Address pipelining for data transfers Jun. 27, 2000
6073198 System for peer-to-peer mastering over a computer bus Jun. 6, 2000
6073199 History-based bus arbitration with hidden re-arbitration during wait cycles Jun. 6, 2000

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