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Class Information
Number: 710/1
Name: Electrical computers and digital data processing systems: input/output > Input/output data processing
Description: Subject matter comprising means or steps for transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5557748 |
Dynamic network configuration |
Sep. 17, 1996 |
| 5555436 |
Apparatus for allowing multiple parallel port devices to share a single parallel port |
Sep. 10, 1996 |
| 5553245 |
Automatic configuration of multiple peripheral interface subsystems in a computer system |
Sep. 3, 1996 |
| 5553300 |
Semiconductor microscope data interface for computer |
Sep. 3, 1996 |
| 5553302 |
Serial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined data |
Sep. 3, 1996 |
| 5550999 |
Information processing system which can check secondary storage medium having prescribed relation therewith and secondary storage device therefor |
Aug. 27, 1996 |
| 5548777 |
Interface control system for a CD-ROM driver by memory mapped I/O method having a predetermined base address using an ISA BUS standard |
Aug. 20, 1996 |
| 5548779 |
System for providing system services for a device to a client using stack definition and stack description of a stack having top, intermediate, and bottom service objects |
Aug. 20, 1996 |
| 5546567 |
System for limiting change in bus clock frequency to duration of I/O operation upon completion signal |
Aug. 13, 1996 |
| 5542046 |
Server entity that provides secure access to its resources through token validation |
Jul. 30, 1996 |
| 5536928 |
System and method for scanning bar codes |
Jul. 16, 1996 |
| 5532844 |
Image data transferring system and method |
Jul. 2, 1996 |
| 5530892 |
Single chassis multiple computer system having separate displays and keyboards with cross interconnect switching for work group coordinator |
Jun. 25, 1996 |
| 5528758 |
Method and apparatus for providing a portable computer with integrated circuit (IC) memory card storage in custom and standard formats |
Jun. 18, 1996 |
| 5526487 |
System for multiprocessor communication |
Jun. 11, 1996 |
| 5515528 |
Computer system having improved idling operation |
May. 7, 1996 |
| 5513372 |
Peripheral interface having hold control logic for generating stall signals to arbitrate two read and one write operations between processor and peripheral |
Apr. 30, 1996 |
| 5511225 |
Programmable controller for controlling output of control system by having configuration circuit cooperating with monitor logic to selectively transmit return output frame |
Apr. 23, 1996 |
| 5509138 |
Method for determining speeds of memory modules |
Apr. 16, 1996 |
| 5504919 |
Sorter structure based on shiftable content memory |
Apr. 2, 1996 |
| 5502839 |
Object-oriented software architecture supporting input/output device independence |
Mar. 26, 1996 |
| 5499341 |
High performance image storage and distribution apparatus having computer bus, high speed bus, ethernet interface, FDDI interface, I/O card, distribution card, and storage units |
Mar. 12, 1996 |
| 5499375 |
Feedback register configuration for a synchronous vector processor employing delayed and non-delayed algorithms |
Mar. 12, 1996 |
| 5499384 |
Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device |
Mar. 12, 1996 |
| 5499379 |
Input/output execution apparatus for a plural-OS run system |
Mar. 12, 1996 |
| 5493689 |
System for configuring an event driven interface including control blocks defining good loop locations in a memory which represent detection of a characteristic pattern |
Feb. 20, 1996 |
| 5491820 |
Distributed, intermittently connected, object-oriented database and management system |
Feb. 13, 1996 |
| 5490282 |
Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing fre |
Feb. 6, 1996 |
| 5490253 |
Multiprocessor system using odd/even data buses with a timeshared address bus |
Feb. 6, 1996 |
| 5481707 |
Dedicated processor for task I/O and memory management |
Jan. 2, 1996 |
| 5479582 |
Message-oriented bank controller interface |
Dec. 26, 1995 |
| H1507 |
Demand assigned multiple access (DAMA) device controller interface |
Dec. 5, 1995 |
| 5471638 |
Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests |
Nov. 28, 1995 |
| 5465038 |
Battery charging/data transfer apparatus for a handheld computer |
Nov. 7, 1995 |
| 5463775 |
System and method for performing monitoring of resources in a data processing system in real time |
Oct. 31, 1995 |
| 5463643 |
Redundant memory channel array configuration with data striping and error correction capabilities |
Oct. 31, 1995 |
| 5459838 |
I/O access method for using flags to selectively control data operation between control unit and I/O channel to allow them proceed independently and concurrently |
Oct. 17, 1995 |
| 5455924 |
Apparatus and method for partial execution blocking of instructions following a data cache miss |
Oct. 3, 1995 |
| 5452470 |
Use of video RAM in high speed data communications |
Sep. 19, 1995 |
| 5452419 |
Serial communication control system between nodes having predetermined intervals for synchronous communications and mediating asynchronous communications for unused time in the predetermined i |
Sep. 19, 1995 |
| 5450546 |
Intelligent hardware for automatically controlling buffer memory storage space in a disk drive |
Sep. 12, 1995 |
| 5448703 |
Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus |
Sep. 5, 1995 |
| 5448704 |
Method for performing writes of non-contiguous bytes on a PCI bus in a minimum number of write cycles |
Sep. 5, 1995 |
| 5446910 |
Interrupt controller with automatic distribution of interrupts for a multiple processor computer system |
Aug. 29, 1995 |
| 5446866 |
Architecture for transferring pixel streams, without control information, in a plurality of formats utilizing addressable source and destination channels associated with the source and destina |
Aug. 29, 1995 |
| 5446904 |
Suspend/resume capability for a protected mode microprocessor |
Aug. 29, 1995 |
| 5442761 |
Method by which packet handler inserts data load instructions in instruction sequence fetched by instruction fetch unit |
Aug. 15, 1995 |
| 5432915 |
Interprocessor communication system in an information processing system enabling communication between execution processor units during communication between other processor units |
Jul. 11, 1995 |
| 5428747 |
Print management system utilizing separate storage units for storing image, edit, and control information relating to prepress jobs thereof |
Jun. 27, 1995 |
| 5428650 |
Method and device for selecting information usable by a local unit connected to a digital transmission system |
Jun. 27, 1995 |
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