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Class Information
Number: 710
Name: Electrical computers and digital data processing systems: input/output >
Description: This class provides, within a computer or digital data processing system, for the following subject matter:










Class Number Class Name No. of Patents
710/240

Access arbitrating

911
710/244

Access prioritizing

535
710/241

Centralized arbitrating

384
710/242

Decentralized arbitrating

163
710/243

Hierarchical or multilevel arbitrating

180
710/200

Access locking

922
710/220

Access polling

158
710/1

Input/output data processing

1073
710/20

Concurrent input/output processing and data transfer

777
710/21

Concurrent data transferring

369
710/33

Data transfer specifying

1344
710/35

Burst data transfer

472
710/34

Transferred data counting

322
710/22

Direct memory accessing (dma)

1702
710/24

By command chaining

238
710/23

Programmed control memory accessing

378
710/25

Timing

248
710/26

Using addressing

355
710/27

Via separate bus

211
710/28

With access regulating

346
710/29

Flow controlling

777
710/30

Frame forming

375
710/36

Input/output access regulation

1553
710/37

Access dedication

222
710/40

Access prioritization

532
710/41

Dynamic

149
710/42

Group

65
710/43

Physical position

59
710/44

Prioritized polling

68
710/45

Time-slot accessing

143
710/39

Access request queuing

524
710/51

Accessing via a multiplexer

190
710/48

Input/output interrupting

467
710/49

Masking

117
710/50

Vectored

61
710/46

Input/output polling

169
710/47

Polled interrupt

67
710/38

Path selection

988
710/3

Input/output addressing

711
710/4

Address data transfer

372
710/5

Input/output command process

2029
710/7

Concurrently performing input/output operation and other operation unrelated to input/output

376
710/6

Operation scheduling

592
710/52

Input/output data buffering

2738
710/53

Alternately filling or emptying buffers

573
710/56

Buffer space allocation or deallocation

835
710/55

Contents validation

245
710/57

Fullness indication

685
710/54

Queue content modification

427
710/2

Input/output expansion

802
710/58

Input/output process timing

689
710/59

Processing suspension

186
710/61

Synchronous data transfer

412
710/60

Transfer rate regulation

503
710/62

Peripheral adapting

2048
710/72

Application-specific peripheral adapting

1018
710/74

For data storage device

983
710/73

For user input device

382
710/65

Input/output data modification

617
710/69

Analog-to-digital or digital-to-analog

185
710/68

Data compression and expansion

428
710/70

Digital-to-digital

57
710/67

Keystroke interpretation

223
710/71

Serial-to-parallel or parallel-to-serial

398
710/66

Width conversion

251
710/63

Universal

430
710/64

Via common units and peripheral-specific units

427
710/8

Peripheral configuration

2839
710/9

Address assignment

803
710/12

As input or output

185
710/13

By detachable memory

283
710/10

Configuration initialization

1455
710/14

Mode selection

895
710/11

Protocol selection

663
710/15

Peripheral monitoring

1711
710/18

Activity monitoring

819
710/17

Availability monitoring

511
710/16

Characteristic discrimination

838
710/19

Status updating

764
710/31

Transfer direction selection

357
710/32

Transfer termination

179
710/260

Interrupt processing

1385
710/269

Handling vector

235
710/262

Interrupt inhibiting or masking

401
710/264

Interrupt prioritizing

354
710/265

Variable

71
710/263

Interrupt queuing

258
710/261

Multimode interrupt processing

318
710/267

Processor status

242
710/266

Programmable interrupt processing

387
710/268

Source or destination identifier

266
710/100

Intrasystem connection (e.g., bus and bus transaction processing)

1725
710/107

Bus access regulation

1379
710/108

Bus locking

200
710/110

Bus master/slave controlling

1045
710/109

Bus polling

126
710/112

Bus request queuing

326
710/113

Centralized bus arbitration

662
710/118

Delay reduction

102
710/116

Dynamic bus prioritization

242
710/114

Static bus prioritization

88
710/115

Physical position bus prioritization

25
710/117

Time-slotted bus accessing

208
710/119

Decentralized bus arbitration

223
710/125

Delay reduction

54
710/123

Dynamic bus prioritization

93
710/120

Hierarchical or multilevel accessing

112
710/121

Static bus prioritization

44
710/122

Physical position bus prioritization

25
710/124

Time-slotted bus accessing

99
710/111

Rotational prioritizing (i.e., round robin)

157
710/300

Bus expansion or extension

779
710/301

Card insertion

1038
710/302

Hot insertion

720
710/303

Docking station

572
710/304

Hot docking

288
710/305

Bus interface architecture

2412
710/306

Bus bridge

1035
710/309

Arbitration

337
710/310

Buffer or que control

785
710/314

Common protocol (e.g., pci to pci)

287
710/315

Different protocol (e.g., pci to isa)

727
710/308

Direct memory access (e.g., dma)

301
710/311

Intelligent bridge

459
710/312

Multiple bridges

233
710/313

Peripheral bus coupling (e.g., pci, usb, isa, and etc.)

969
710/307

Variable or multiple bus width

436
710/316

Path selecting switch

1215
710/317

Crossbar

446
710/105

Protocol

1126
710/106

Using transmitter and receiver

503
710/104

System configuring

1476
 
 
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