Electrical computers and digital data processing systems: input/output > Patents

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Class Information
Number: 710
Name: Electrical computers and digital data processing systems: input/output >
Description: This class provides, within a computer or digital data processing system, for the following subject matter:

Class Number	Class Name	No. of Patents
710/240	Access arbitrating	694
710/244	Access prioritizing	401
710/241	Centralized arbitrating	293
710/242	Decentralized arbitrating	122
710/243	Hierarchical or multilevel arbitrating	129
710/200	Access locking	700
710/220	Access polling	132
710/1	Input/output data processing	812
710/20	Concurrent input/output processing and data transfer	539
710/21	Concurrent data transferring	283
710/33	Data transfer specifying	848
710/35	Burst data transfer	367
710/34	Transferred data counting	227
710/22	Direct memory accessing (dma)	1136
710/24	By command chaining	154
710/23	Programmed control memory accessing	272
710/25	Timing	188
710/26	Using addressing	248
710/27	Via separate bus	158
710/28	With access regulating	238
710/29	Flow controlling	517
710/30	Frame forming	245
710/36	Input/output access regulation	982
710/37	Access dedication	164
710/40	Access prioritization	404
710/41	Dynamic	122
710/42	Group	42
710/43	Physical position	48
710/44	Prioritized polling	50
710/45	Time-slot accessing	114
710/39	Access request queuing	401
710/51	Accessing via a multiplexer	130
710/48	Input/output interrupting	388
710/49	Masking	98
710/50	Vectored	44
710/46	Input/output polling	134
710/47	Polled interrupt	49
710/38	Path selection	673
710/3	Input/output addressing	497
710/4	Address data transfer	268
710/5	Input/output command process	1238
710/7	Concurrently performing input/output operation and other operation unrelated to input/output	255
710/6	Operation scheduling	425
710/52	Input/output data buffering	1969
710/53	Alternately filling or emptying buffers	445
710/56	Buffer space allocation or deallocation	619
710/55	Contents validation	180
710/57	Fullness indication	528
710/54	Queue content modification	312
710/2	Input/output expansion	509
710/58	Input/output process timing	494
710/59	Processing suspension	126
710/61	Synchronous data transfer	319
710/60	Transfer rate regulation	369
710/62	Peripheral adapting	1232
710/72	Application-specific peripheral adapting	725
710/74	For data storage device	573
710/73	For user input device	262
710/65	Input/output data modification	460
710/69	Analog-to-digital or digital-to-analog	135
710/68	Data compression and expansion	324
710/70	Digital-to-digital	43
710/67	Keystroke interpretation	136
710/71	Serial-to-parallel or parallel-to-serial	284
710/66	Width conversion	192
710/63	Universal	321
710/64	Via common units and peripheral-specific units	299
710/8	Peripheral configuration	1696
710/9	Address assignment	569
710/12	As input or output	123
710/13	By detachable memory	205
710/10	Configuration initialization	1017
710/14	Mode selection	557
710/11	Protocol selection	433
710/15	Peripheral monitoring	939
710/18	Activity monitoring	500
710/17	Availability monitoring	279
710/16	Characteristic discrimination	483
710/19	Status updating	452
710/31	Transfer direction selection	240
710/32	Transfer termination	106
710/260	Interrupt processing	1062
710/269	Handling vector	181
710/262	Interrupt inhibiting or masking	297
710/264	Interrupt prioritizing	292
710/265	Variable	53
710/263	Interrupt queuing	195
710/261	Multimode interrupt processing	242
710/267	Processor status	156
710/266	Programmable interrupt processing	313
710/268	Source or destination identifier	192
710/100	Intrasystem connection (e.g., bus and bus transaction processing)	1406
710/107	Bus access regulation	1153
710/108	Bus locking	177
710/110	Bus master/slave controlling	697
710/109	Bus polling	104
710/112	Bus request queuing	291
710/113	Centralized bus arbitration	577
710/118	Delay reduction	87
710/116	Dynamic bus prioritization	198
710/114	Static bus prioritization	80
710/115	Physical position bus prioritization	21
710/117	Time-slotted bus accessing	153
710/119	Decentralized bus arbitration	194
710/125	Delay reduction	48
710/123	Dynamic bus prioritization	80
710/120	Hierarchical or multilevel accessing	92
710/121	Static bus prioritization	38
710/122	Physical position bus prioritization	21
710/124	Time-slotted bus accessing	79
710/111	Rotational prioritizing (i.e., round robin)	132
710/300	Bus expansion or extension	541
710/301	Card insertion	727
710/302	Hot insertion	538
710/303	Docking station	367
710/304	Hot docking	158
710/305	Bus interface architecture	1766
710/306	Bus bridge	730
710/309	Arbitration	268
710/310	Buffer or que control	594
710/314	Common protocol (e.g., pci to pci)	202
710/315	Different protocol (e.g., pci to isa)	499
710/308	Direct memory access (e.g., dma)	200
710/311	Intelligent bridge	298
710/312	Multiple bridges	170
710/313	Peripheral bus coupling (e.g., pci, usb, isa, and etc.)	572
710/307	Variable or multiple bus width	366
710/316	Path selecting switch	777
710/317	Crossbar	319
710/105	Protocol	775
710/106	Using transmitter and receiver	348
710/104	System configuring	1084