| |
 |
|
Class Information
Number: 708/700
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Addition/subtraction > Binary
Description: Subject matter wherein the numerical digits are of radix two.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617269 |
Logic entity with two outputs for efficient adder and other macro implementations |
Nov. 10, 2009 |
| 7475105 |
One bit full adder with sum and carry outputs capable of independent functionalities |
Jan. 6, 2009 |
| 7401110 |
System, method and apparatus for an improved MD5 hash algorithm |
Jul. 15, 2008 |
| 7395306 |
Fast add rotate add operation |
Jul. 1, 2008 |
| 7386583 |
Carry generator based on XOR, and conditional select adder using the carry generator, and method therefor |
Jun. 10, 2008 |
| 7302460 |
Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic |
Nov. 27, 2007 |
| 7290026 |
Low-power high-speed 4-2 compressor with minimized transistor count |
Oct. 30, 2007 |
| 7266581 |
Arithmetic circuit |
Sep. 4, 2007 |
| 7231414 |
Apparatus and method for performing addition of PKG recoded numbers |
Jun. 12, 2007 |
| 7218139 |
Programmable integrated circuit providing efficient implementations of arithmetic functions |
May. 15, 2007 |
| 7085796 |
Dynamic adder with reduced logic |
Aug. 1, 2006 |
| 7024446 |
Circuitry for arithmetically accumulating a succession of arithmetic values |
Apr. 4, 2006 |
| 6999985 |
Single instruction multiple data processing |
Feb. 14, 2006 |
| 6990508 |
High performance carry chain with reduced macrocell logic and fast carry lookahead |
Jan. 24, 2006 |
| 6924664 |
Field programmable gate array |
Aug. 2, 2005 |
| 6847228 |
Carry logic design having simplified timing modeling for a field programmable gate array |
Jan. 25, 2005 |
| 6832315 |
Method of labelling an article |
Dec. 14, 2004 |
| 6820186 |
System and method for building packets |
Nov. 16, 2004 |
| 6775801 |
Turbo decoder extrinsic normalization |
Aug. 10, 2004 |
| 6772187 |
Parallel greater than analysis method and apparatus |
Aug. 3, 2004 |
| 6769007 |
Adder circuit with a regular structure |
Jul. 27, 2004 |
| 6711604 |
Binary adder |
Mar. 23, 2004 |
| 6658446 |
Fast chainable carry look-ahead adder |
Dec. 2, 2003 |
| 6647405 |
Adder circuit, integrating circuit which uses the adder circuit, and synchronism detection circuit which uses the integrating circuit |
Nov. 11, 2003 |
| 6625634 |
Efficient implementation of multiprecision arithmetic |
Sep. 23, 2003 |
| 6539413 |
Prefix tree adder with efficient sum generation |
Mar. 25, 2003 |
| 6480874 |
Power saving method for performing additions and subtractions and a device thereof |
Nov. 12, 2002 |
| 6470373 |
Sum interval detector |
Oct. 22, 2002 |
| 6470374 |
Carry look-ahead for bi-endian adder |
Oct. 22, 2002 |
| 6343306 |
High speed one's complement adder |
Jan. 29, 2002 |
| 6101523 |
Method and apparatus for controlling calculation error |
Aug. 8, 2000 |
| 6055557 |
Adder circuit and method therefor |
Apr. 25, 2000 |
| 6041341 |
Method and circuit for adding operands of multiple size |
Mar. 21, 2000 |
| 5995994 |
Calculating A -sign(A) in a single instruction cycle |
Nov. 30, 1999 |
| 5959874 |
Method and apparatus for inserting control digits into packed data to perform packed arithmetic operations |
Sep. 28, 1999 |
| 5951630 |
Digital adder circuit |
Sep. 14, 1999 |
| 5935203 |
Rectifying transfer gate circuit |
Aug. 10, 1999 |
| 5907500 |
Motion compensation adder for decoding/decompressing compressed moving pictures |
May. 25, 1999 |
| 5905667 |
Full adder using NMOS transistor |
May. 18, 1999 |
| 5856936 |
Calculating A - sign(A) in a single instruction cycle |
Jan. 5, 1999 |
| 5850347 |
Calculating 2A+ sign(A) in a single instruction cycle |
Dec. 15, 1998 |
| 5847983 |
Full subtracter |
Dec. 8, 1998 |
| 5835394 |
Calculating selected sign 3 expression in a single instruction cycle |
Nov. 10, 1998 |
| 5831887 |
Calculating 2A-sign(A) in a single instruction cycle |
Nov. 3, 1998 |
| 5831886 |
Calculating a + sign(A) in a single instruction cycle |
Nov. 3, 1998 |
| 5822235 |
Rectifying transfer gate circuit |
Oct. 13, 1998 |
| 5805490 |
Associative memory circuit and TLB circuit |
Sep. 8, 1998 |
| 5798952 |
Leading bit anticipator |
Aug. 25, 1998 |
| 5793662 |
Null convention adder |
Aug. 11, 1998 |
| 5777918 |
Fast multiple operands adder/subtracter based on shifting |
Jul. 7, 1998 |
|
|
|
