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Class Information
Number: 708/670
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Addition/subtraction
Description: Subject matter wherein the arithmetic operation performed is addition or subtraction.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7592835 |
Co-processor having configurable logic blocks |
Sep. 22, 2009 |
| 7555514 |
Packed add-subtract operation in a microprocessor |
Jun. 30, 2009 |
| 7428567 |
Arithmetic unit for addition or subtraction with preliminary saturation detection |
Sep. 23, 2008 |
| 7424507 |
High speed, low power, pipelined zero crossing detector that utilizes carry save adders |
Sep. 9, 2008 |
| 7395302 |
Method and apparatus for performing horizontal addition and subtraction |
Jul. 1, 2008 |
| 7376691 |
Arithmetic and logic unit using half adder |
May. 20, 2008 |
| 7373369 |
Advanced execution of extended floating-point add operations in a narrow dataflow |
May. 13, 2008 |
| 7356554 |
Variable fixed multipliers using memory blocks |
Apr. 8, 2008 |
| 7322032 |
Methods and apparatus for scheduling operation of a data source |
Jan. 22, 2008 |
| 7228325 |
Bypassable adder |
Jun. 5, 2007 |
| 7225218 |
Apparatus and methods for generating counts from base values |
May. 29, 2007 |
| 7213043 |
Sparce-redundant fixed point arithmetic modules |
May. 1, 2007 |
| 7197528 |
Jacobian group element adder |
Mar. 27, 2007 |
| 7164290 |
Field programmable gate array logic unit and its cluster |
Jan. 16, 2007 |
| 7155473 |
High-speed parallel-prefix modulo 2n-1 adders |
Dec. 26, 2006 |
| 7139900 |
Data packet arithmetic logic devices and methods |
Nov. 21, 2006 |
| 7111166 |
Extending the range of computational fields of integers |
Sep. 19, 2006 |
| 7061268 |
Initializing a carry chain in a programmable logic device |
Jun. 13, 2006 |
| 7058678 |
Fast forwarding ALU |
Jun. 6, 2006 |
| 7013036 |
Image sensing apparatus and method of controlling image sensing |
Mar. 14, 2006 |
| 6988121 |
Efficient implementation of multiprecision arithmetic |
Jan. 17, 2006 |
| 6963893 |
Methods of factoring and modular arithmetic |
Nov. 8, 2005 |
| 6943579 |
Variable fixed multipliers using memory blocks |
Sep. 13, 2005 |
| 6918024 |
Address generating circuit and selection judging circuit |
Jul. 12, 2005 |
| 6877069 |
History-based carry predictor for data cache address generation |
Apr. 5, 2005 |
| 6868432 |
Addition circuit for digital data with a delayed saturation operation for the most significant data bits |
Mar. 15, 2005 |
| 6836147 |
Function block |
Dec. 28, 2004 |
| 6832234 |
In-place associative processor arithmetic |
Dec. 14, 2004 |
| 6757703 |
Associative processor addition and subtraction |
Jun. 29, 2004 |
| 6754689 |
Method and apparatus for performing subtraction in redundant form arithmetic |
Jun. 22, 2004 |
| 6742013 |
Apparatus and method for uniformly performing comparison operations on long word operands |
May. 25, 2004 |
| 6668268 |
Method and apparatus for compiling dependent subtraction operations on arithmetic intervals |
Dec. 23, 2003 |
| 6591285 |
Running-sum adder networks determined by recursive construction of multi-stage networks |
Jul. 8, 2003 |
| 6584156 |
LSI Architecture and implementation of MPEG video codec |
Jun. 24, 2003 |
| 6557097 |
Linear vector computation |
Apr. 29, 2003 |
| 6546410 |
High-speed hexadecimal adding method and system |
Apr. 8, 2003 |
| 6542918 |
Prefix sums and an application thereof |
Apr. 1, 2003 |
| 6505225 |
Adder logic circuit and processor |
Jan. 7, 2003 |
| 6493263 |
Semiconductor computing circuit and computing apparatus |
Dec. 10, 2002 |
| 6460066 |
50 MHz 40-bit accumulator with trigger capability |
Oct. 1, 2002 |
| 6446106 |
Seed ROM for reciprocal computation |
Sep. 3, 2002 |
| 6405233 |
Unaligned semaphore adder |
Jun. 11, 2002 |
| 6374281 |
Adder |
Apr. 16, 2002 |
| 6369610 |
Reconfigurable multiplier array |
Apr. 9, 2002 |
| 6363408 |
Method and apparatus for summing selected bits from a plurality of machine vectors |
Mar. 26, 2002 |
| 6334136 |
Dynamic 3-level partial result merge adder |
Dec. 25, 2001 |
| 6330581 |
Apparatus and a method for address generation |
Dec. 11, 2001 |
| 6301597 |
Method and apparatus for saturation in an N-NARY adder/subtractor |
Oct. 9, 2001 |
| 6301600 |
Method and apparatus for dynamic partitionable saturating adder/subtractor |
Oct. 9, 2001 |
| 6240338 |
Seed ROM for reciprocal computation |
May. 29, 2001 |
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