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Class Information
Number: 708/620
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Multiplication
Description: Subject matter wherein the arithmetic operation performed is multiplication.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620677 |
4:2 Carry save adder and 4:2 carry save adding method |
Nov. 17, 2009 |
| 7595659 |
Logic cell array and bus system |
Sep. 29, 2009 |
| 7587443 |
Digital signal processor with efficient multi-modal multiplier |
Sep. 8, 2009 |
| 7564971 |
Apparatus and method for performing Montgomery type modular multiplication |
Jul. 21, 2009 |
| 7565391 |
Binary digit multiplications and applications |
Jul. 21, 2009 |
| 7562106 |
Multi-value digital calculating circuits, including multipliers |
Jul. 14, 2009 |
| 7539714 |
Method, apparatus, and instruction for performing a sign operation that multiplies |
May. 26, 2009 |
| 7519643 |
Montgomery multiplier for RSA security module |
Apr. 14, 2009 |
| 7519646 |
Reconfigurable SIMD vector processing system |
Apr. 14, 2009 |
| 7506016 |
Multiplier device |
Mar. 17, 2009 |
| 7506017 |
Verifiable multimode multipliers |
Mar. 17, 2009 |
| 7487196 |
Methods and apparatus for implementing a saturating multiplier |
Feb. 3, 2009 |
| 7418468 |
Low-voltage CMOS circuits for analog decoders |
Aug. 26, 2008 |
| 7395300 |
System, and method for calculating product of constant and mixed number power of two |
Jul. 1, 2008 |
| 7395299 |
System and method for efficient hardware implementation of a perfect precision blending function |
Jul. 1, 2008 |
| 7389317 |
Long instruction word controlling plural independent processor operations |
Jun. 17, 2008 |
| 7266579 |
Combined polynomial and natural multiplier architecture |
Sep. 4, 2007 |
| 7240204 |
Scalable and unified multiplication methods and apparatus |
Jul. 3, 2007 |
| 7213043 |
Sparce-redundant fixed point arithmetic modules |
May. 1, 2007 |
| 7212959 |
Method and apparatus for accumulating floating point values |
May. 1, 2007 |
| 7206801 |
Digital multiplier with reduced spurious switching by means of Latch Adders |
Apr. 17, 2007 |
| 7200194 |
Receiver signal dynamic range compensation based on received signal strength indicator |
Apr. 3, 2007 |
| 7194498 |
Higher radix multiplier with simplified partial product generator |
Mar. 20, 2007 |
| 7177894 |
Switching activity reduced coding for low-power digital signal processing circuitry |
Feb. 13, 2007 |
| 7159004 |
Adder, multiplier and integrated circuit |
Jan. 2, 2007 |
| 7080114 |
High speed scaleable multiplier |
Jul. 18, 2006 |
| 7062526 |
Microprocessor with rounding multiply instructions |
Jun. 13, 2006 |
| 7024444 |
Split multiplier array and method of operation |
Apr. 4, 2006 |
| 6993551 |
Sparse-coefficient functions for reducing computational requirements |
Jan. 31, 2006 |
| 6993550 |
Fixed point multiplying apparatus and method using encoded multiplicand |
Jan. 31, 2006 |
| 6993071 |
Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers |
Jan. 31, 2006 |
| 6959316 |
Dynamically configurable processor |
Oct. 25, 2005 |
| 6950840 |
Noise invariant circuits, systems and methods |
Sep. 27, 2005 |
| 6940920 |
Multiplier arrangement, signal modulator and transmitter |
Sep. 6, 2005 |
| 6934728 |
Euclidean distance instructions |
Aug. 23, 2005 |
| 6922717 |
Method and apparatus for performing modular multiplication |
Jul. 26, 2005 |
| 6915322 |
Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands |
Jul. 5, 2005 |
| 6901423 |
Noise invariant circuits, systems and methods |
May. 31, 2005 |
| 6877022 |
Booth encoding circuit for a multiplier of a multiply-accumulate module |
Apr. 5, 2005 |
| 6839728 |
Efficient complex multiplication and fast fourier transform (FFT) implementation on the manarray architecture |
Jan. 4, 2005 |
| 6813627 |
Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands |
Nov. 2, 2004 |
| 6763367 |
Pre-reduction technique within a multiplier/accumulator architecture |
Jul. 13, 2004 |
| 6742011 |
Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry |
May. 25, 2004 |
| 6708193 |
Linear summation multiplier array implementation for both signed and unsigned multiplication |
Mar. 16, 2004 |
| 6684236 |
System of and method for efficiently performing computations through extended booth encoding of the operands thereto |
Jan. 27, 2004 |
| 6675186 |
Decibel adjustment device with shift amount control circuit |
Jan. 6, 2004 |
| 6633896 |
Method and system for multiplying large numbers |
Oct. 14, 2003 |
| 6629119 |
Arithmetic device and method with low power consumption |
Sep. 30, 2003 |
| 6629120 |
Method and apparatus for performing a mask-driven interval multiplication operation |
Sep. 30, 2003 |
| 6622154 |
Alternate booth partial product generation for a hardware multiplier |
Sep. 16, 2003 |
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