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Class Information
Number: 708/551
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Compensation for finite word length > Round off or truncation
Description: Subject matter wherein the modification is an adjustment of the more significant digits in accordance with some specific rule or a deletion of one or more of the least significant digits.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6055555 |
Interface for performing parallel arithmetic and round operations |
Apr. 25, 2000 |
| 6044392 |
Method and apparatus for performing rounding in a data processor |
Mar. 28, 2000 |
| 6038583 |
Method and apparatus for simultaneously multiplying two or more independent pairs of operands and calculating a rounded products |
Mar. 14, 2000 |
| 6012076 |
Arithmetic logic unit having preshift and preround circuits |
Jan. 4, 2000 |
| 5995992 |
Conditional truncation indicator control for a decimal numeric processor employing result truncation |
Nov. 30, 1999 |
| 5974432 |
On-the-fly one-hot encoding of leading zero count |
Oct. 26, 1999 |
| 5974540 |
Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing |
Oct. 26, 1999 |
| 5941941 |
Bit width controlling method |
Aug. 24, 1999 |
| 5917741 |
Method and apparatus for performing floating-point rounding operations for multiple precisions using incrementers |
Jun. 29, 1999 |
| 5912909 |
Method and apparatus for efficient implementation of checksum calculations |
Jun. 15, 1999 |
| 5894428 |
Recursive digital filter |
Apr. 13, 1999 |
| 5781464 |
Apparatus and method for incrementing floating-point numbers represented in diffrent precision modes |
Jul. 14, 1998 |
| 5737255 |
Method and system of rounding for quadratically converging division or square root |
Apr. 7, 1998 |
| 5729481 |
Method and system of rounding for quadratically converging division or square root |
Mar. 17, 1998 |
| 5696710 |
Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal |
Dec. 9, 1997 |
| 5696709 |
Program controlled rounding modes |
Dec. 9, 1997 |
| 5644522 |
Method, apparatus and system for multiply rounding using redundant coded multiply result |
Jul. 1, 1997 |
| 5633818 |
Method and apparatus for performing floating point arithmetic operation and rounding the result thereof |
May. 27, 1997 |
| 5619440 |
Multiplier circuit with rounding-off function |
Apr. 8, 1997 |
| 5604494 |
Efficient encoding/decoding apparatus |
Feb. 18, 1997 |
| 5600584 |
Interactive formula compiler and range estimator |
Feb. 4, 1997 |
| 5574676 |
Integer multiply instructions incorporating a subresult selection option |
Nov. 12, 1996 |
| 5561615 |
Method and apparatus for floating point to fixed point conversion with compensation for lost precision |
Oct. 1, 1996 |
| 5500812 |
Multiplication circuit having rounding function |
Mar. 19, 1996 |
| 5479454 |
Digital filter with improved numerical precision |
Dec. 26, 1995 |
| 5463575 |
Reduced quantization noise from single-precision multiplier |
Oct. 31, 1995 |
| 5463570 |
Digital data rounding |
Oct. 31, 1995 |
| 5428567 |
Memory structure to minimize rounding/trunction errors for n-dimensional image transformation |
Jun. 27, 1995 |
| 5424967 |
Shift and rounding circuit and method |
Jun. 13, 1995 |
| 5329475 |
Data round-off device for rounding-off m-bit digital data into (m-n) bit digital data |
Jul. 12, 1994 |
| 5317530 |
Rounding operation circuit |
May. 31, 1994 |
| 5218563 |
Data round-off device for rounding-off m-bit digital data into (m-n)-bit digital data |
Jun. 8, 1993 |
| 5214598 |
Unbiased bit disposal apparatus and method |
May. 25, 1993 |
| 5208770 |
Accumulation circuit having a round-off function |
May. 4, 1993 |
| 5204832 |
Addition apparatus having round-off function |
Apr. 20, 1993 |
| 5198993 |
Arithmetic device having a plurality of partitioned adders |
Mar. 30, 1993 |
| 5170371 |
Method and apparatus for rounding in high-speed multipliers |
Dec. 8, 1992 |
| 5128887 |
Numerical accuracy indicator for rounded numeric value display method |
Jul. 7, 1992 |
| 4965668 |
Adaptive rounder for video signals |
Oct. 23, 1990 |
| 4945507 |
Overflow correction circuit |
Jul. 31, 1990 |
| 4853886 |
Digital signal processing circuit |
Aug. 1, 1989 |
| 4841468 |
High-speed digital multiplier architecture |
Jun. 20, 1989 |
| 4823260 |
Mixed-precision floating point operations from a single instruction opcode |
Apr. 18, 1989 |
| 4809207 |
Recursive first order digital video signal filter |
Feb. 28, 1989 |
| 4755961 |
Digital tank circuit |
Jul. 5, 1988 |
| 4750146 |
Method and apparatus for compensating for the truncation error in a filtered signal by adding the error to the positive part of the signal and subtracting the error from the negative part of t |
Jun. 7, 1988 |
| 4727506 |
Digital scaling circuitry with truncation offset compensation |
Feb. 23, 1988 |
| 4648058 |
Look-ahead rounding circuit |
Mar. 3, 1987 |
| 4589084 |
Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals |
May. 13, 1986 |
| 4511922 |
Digital television system with truncation error correction |
Apr. 16, 1985 |
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