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Class Information
Number: 708/550
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Compensation for finite word length
Description: Subject matter wherein the operation results in a word modification in length due to insufficient representation of using the fixed word length of the arithmetic system.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7577699 |
Apparatus and method for reducing precision of data |
Aug. 18, 2009 |
| 7130876 |
Systems and methods for efficient quantization |
Oct. 31, 2006 |
| 7085794 |
Low power vector summation method and apparatus |
Aug. 1, 2006 |
| 7080115 |
Low-error canonic-signed-digit fixed-width multiplier, and method for designing same |
Jul. 18, 2006 |
| 7062526 |
Microprocessor with rounding multiply instructions |
Jun. 13, 2006 |
| 7035892 |
Apparatus and method for reducing precision of data |
Apr. 25, 2006 |
| 6996597 |
Increasing precision in multi-stage processing of digital signals |
Feb. 7, 2006 |
| 6957244 |
Reduced-width low-error multiplier |
Oct. 18, 2005 |
| 6879992 |
System and method to efficiently round real numbers |
Apr. 12, 2005 |
| 6874007 |
Apparatus and method for reducing precision of data |
Mar. 29, 2005 |
| 6801925 |
Bit reduction using dither, rounding and error feedback |
Oct. 5, 2004 |
| 6792442 |
Signal processor and product-sum operating device for use therein with rounding function |
Sep. 14, 2004 |
| 6728739 |
Data calculating device and method for processing data in data block form |
Apr. 27, 2004 |
| 6529929 |
Quantization device and method using prime number dividers |
Mar. 4, 2003 |
| 6401194 |
Execution unit for processing a data stream independently and in parallel |
Jun. 4, 2002 |
| 6334202 |
Fast metric calculation for Viterbi decoder implementation |
Dec. 25, 2001 |
| 6298368 |
Method and apparatus for efficient calculation of an approximate square of a fixed-precision number |
Oct. 2, 2001 |
| 6148319 |
Multiplier |
Nov. 14, 2000 |
| 6115732 |
Method and apparatus for compressing intermediate products |
Sep. 5, 2000 |
| 6101521 |
Data processing method and apparatus operable on an irrational mathematical value |
Aug. 8, 2000 |
| 6058410 |
Method and apparatus for selecting a rounding mode for a numeric operation |
May. 2, 2000 |
| 5930159 |
Right-shifting an integer operand and rounding a fractional intermediate result to obtain a rounded integer result |
Jul. 27, 1999 |
| 5892697 |
Method and apparatus for handling overflow and underflow in processing floating-point numbers |
Apr. 6, 1999 |
| 5887181 |
Method and apparatus for reducing a computational result to the range boundaries of an unsigned 8-bit integer in case of overflow |
Mar. 23, 1999 |
| 5835887 |
Process for the rapid digital acquisition and processing of analogue measured values in a processor with restricted binary word length |
Nov. 10, 1998 |
| 5809292 |
Floating point for simid array machine |
Sep. 15, 1998 |
| 5771183 |
Apparatus and method for computation of sticky bit in a multi-stage shifter used for floating point arithmetic |
Jun. 23, 1998 |
| 5764990 |
Compact encoding for storing integer multiplication Sequences |
Jun. 9, 1998 |
| 5751902 |
Adaptive prediction filter using block floating point format and minimal recursive recomputations |
May. 12, 1998 |
| 5734879 |
Saturation instruction in a data processor |
Mar. 31, 1998 |
| 5726927 |
Multiply pipe round adder |
Mar. 10, 1998 |
| 5652862 |
Method and appartus for determining a precision of an intermediate arithmetic for converting values between a first numeric format and a second numeric format |
Jul. 29, 1997 |
| 5633815 |
Formatter |
May. 27, 1997 |
| 5629881 |
Method for filtering a digital value train with improved noise behavior, and circuit configuration for performing the method |
May. 13, 1997 |
| 5619711 |
Method and data processing system for arbitrary precision on numbers |
Apr. 8, 1997 |
| 5612909 |
Method and apparatus for rounding operands using previous rounding history |
Mar. 18, 1997 |
| 5515520 |
Data processing system for single-precision and double-precision data |
May. 7, 1996 |
| 5432726 |
Arithmetic unit for quantization/inverse quantigation |
Jul. 11, 1995 |
| 4722068 |
Double precision multiplier |
Jan. 26, 1988 |
| 4598382 |
Multiplying circuit |
Jul. 1, 1986 |
| 4475237 |
Programmable range recognizer for a logic analyzer |
Oct. 2, 1984 |
| 4449196 |
Data processing system for multi-precision arithmetic |
May. 15, 1984 |
| 4340940 |
Hardware reduction by truncation of selected number of most significant bits for digital video system using subsampling and adaptive reconstruction |
Jul. 20, 1982 |
| 4272827 |
Division processing method system having 2N-bit precision |
Jun. 9, 1981 |
| 4272648 |
Gain control apparatus for digital telephone line circuits |
Jun. 9, 1981 |
| 4213187 |
Digital filters with control of limit cycles |
Jul. 15, 1980 |
| 4110831 |
Method and means for tracking digit significance in arithmetic operations executed on decimal computers |
Aug. 29, 1978 |
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