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Class Information
Number: 708/518
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Variable length
Description: Subject matter wherein the number of numerical digits that represent numbers are of differing length.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7366305 |
Platform and method for establishing trust without revealing identity |
Apr. 29, 2008 |
| 7219118 |
SIMD addition circuit |
May. 15, 2007 |
| 7149768 |
3-input arithmetic logic unit |
Dec. 12, 2006 |
| 6883012 |
Linear-to-log converter for power estimation in a wireless data network receiver |
Apr. 19, 2005 |
| 6813627 |
Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands |
Nov. 2, 2004 |
| 6795841 |
Parallel processing of multiple data values within a data word |
Sep. 21, 2004 |
| 6748411 |
Hierarchical carry-select multiple-input split adder |
Jun. 8, 2004 |
| 6732126 |
High performance datapath unit for behavioral data transmission and reception |
May. 4, 2004 |
| 6725360 |
Selectively processing different size data in multiplier and ALU paths in parallel |
Apr. 20, 2004 |
| 6557096 |
Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types |
Apr. 29, 2003 |
| 6557020 |
Information processing system, enciphering/deciphering system, system LSI, and electronic apparatus |
Apr. 29, 2003 |
| 6502119 |
High speed microprocessor zero detection circuit with 32-bit and 64-bit modes |
Dec. 31, 2002 |
| 6460064 |
Multiplier for operating n bits and n/2 bits and method therefor |
Oct. 1, 2002 |
| 6449629 |
Three input split-adder |
Sep. 10, 2002 |
| 6408320 |
Instruction set architecture with versatile adder carry control |
Jun. 18, 2002 |
| 6301600 |
Method and apparatus for dynamic partitionable saturating adder/subtractor |
Oct. 9, 2001 |
| 6260055 |
Data split parallel shifter and parallel adder/subtractor |
Jul. 10, 2001 |
| 6253299 |
Virtual cache registers with selectable width for accommodating different precision data formats |
Jun. 26, 2001 |
| 6202077 |
SIMD data processing extended precision arithmetic operand format |
Mar. 13, 2001 |
| 6188240 |
Programmable function block |
Feb. 13, 2001 |
| 6041341 |
Method and circuit for adding operands of multiple size |
Mar. 21, 2000 |
| 6035318 |
Booth multiplier for handling variable width operands |
Mar. 7, 2000 |
| 6032170 |
Long instruction word controlling plural independent processor operations |
Feb. 29, 2000 |
| 6003125 |
High performance adder for multiple parallel add operations |
Dec. 14, 1999 |
| 5991868 |
Apparatus and method for processing data with a plurality of flag groups |
Nov. 23, 1999 |
| 5959874 |
Method and apparatus for inserting control digits into packed data to perform packed arithmetic operations |
Sep. 28, 1999 |
| 5943251 |
Adder which handles multiple data with different data types |
Aug. 24, 1999 |
| 5886914 |
Filter circuit with reduced number of delay elements and adders |
Mar. 23, 1999 |
| 5883824 |
Parallel adding and averaging circuit and method |
Mar. 16, 1999 |
| 5880979 |
System for providing the absolute difference of unsigned values |
Mar. 9, 1999 |
| 5844826 |
Leading zero count circuit |
Dec. 1, 1998 |
| 5822223 |
Electronic foot measuring apparatus |
Oct. 13, 1998 |
| 5757685 |
Data processing system capable of processing long word data |
May. 26, 1998 |
| 5748515 |
Data processing condition code flags |
May. 5, 1998 |
| 5742529 |
Method and an apparatus for providing the absolute difference of unsigned values |
Apr. 21, 1998 |
| 5727225 |
Method, apparatus and system forming the sum of data in plural equal sections of a single data word |
Mar. 10, 1998 |
| 5719802 |
Adder circuit incorporating byte boundaries |
Feb. 17, 1998 |
| 5699279 |
Optimized binary adders and comparators for inputs having different widths |
Dec. 16, 1997 |
| 5677862 |
Method for multiplying packed data |
Oct. 14, 1997 |
| 5675526 |
Processor performing packed data multiplication |
Oct. 7, 1997 |
| 5649147 |
Circuit for designating instruction pointers for use by a processor decoder |
Jul. 15, 1997 |
| 5638312 |
Method and apparatus for generating a zero bit status flag in a microprocessor |
Jun. 10, 1997 |
| 5625582 |
Apparatus and method for optimizing address calculations |
Apr. 29, 1997 |
| 5625713 |
Apparatus and method for increasing the throughput of an acoustic or image compression system |
Apr. 29, 1997 |
| 5615402 |
Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch |
Mar. 25, 1997 |
| 5615140 |
Fixed-point arithmetic unit |
Mar. 25, 1997 |
| 5592405 |
Multiple operations employing divided arithmetic logic unit and multiple flags register |
Jan. 7, 1997 |
| 5530661 |
Data bit-slicing apparatus and method for computing convolutions |
Jun. 25, 1996 |
| 5517440 |
Optimized binary adders and comparators for inputs having different widths |
May. 14, 1996 |
| 5479365 |
Exponentiation remainder operation circuit |
Dec. 26, 1995 |
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