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Class Information
Number: 708/514
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Floating point > Matrix array
Description: Subject matter wherein the data is operated on by elements arranged in rows and columns.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7567996 |
Vector SIMD processor |
Jul. 28, 2009 |
| 7363200 |
Apparatus and method for isolating noise effects in a signal |
Apr. 22, 2008 |
| 7137005 |
Method of watermarking digital data |
Nov. 14, 2006 |
| 7089159 |
Method and apparatus for matrix reordering and electronic circuit simulation |
Aug. 8, 2006 |
| 7028066 |
Vector SIMD processor |
Apr. 11, 2006 |
| 7010760 |
Batch-based method and tool for graphical manipulation of workflows |
Mar. 7, 2006 |
| 6820074 |
Null-line based radial interpolation of gridded data |
Nov. 16, 2004 |
| 6662125 |
Electromagnetic wave analyzer and program for same |
Dec. 9, 2003 |
| 6188240 |
Programmable function block |
Feb. 13, 2001 |
| 6009505 |
System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot |
Dec. 28, 1999 |
| 5859790 |
Replication of data |
Jan. 12, 1999 |
| 5268856 |
Bit serial floating point parallel processing system and method |
Dec. 7, 1993 |
| 5121351 |
Floating point arithmetic system |
Jun. 9, 1992 |
| 5025407 |
Graphics floating point coprocessor having matrix capabilities |
Jun. 18, 1991 |
| 4996661 |
Single chip complex floating point numeric processor |
Feb. 26, 1991 |
| 4956801 |
Matrix arithmetic circuit for processing matrix transformation operations |
Sep. 11, 1990 |
| 4888682 |
Parallel vector processor using multiple dedicated processors and vector registers divided into smaller registers |
Dec. 19, 1989 |
| 4884190 |
High performance parallel vector processor having a modified vector register/element processor configuration |
Nov. 28, 1989 |
| 4736335 |
Multiplier-accumulator circuit using latched sums and carries |
Apr. 5, 1988 |
| 4683547 |
Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance |
Jul. 28, 1987 |
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