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Class Information
Number: 708/508
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Floating point > Pipeline
Description: Subject matter wherein the operation is effected by passing the output of one task as input to another until a desired sequence of tasks has been carried out.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7490221 |
Synchronization between pipelines in a data processing apparatus utilizing a synchronization queue |
Feb. 10, 2009 |
| 7406589 |
Processor having efficient function estimate instructions |
Jul. 29, 2008 |
| 7043516 |
Reduction of add-pipe logic by operand offset shift |
May. 9, 2006 |
| 6748521 |
Microprocessor with instruction for saturating and packing data |
Jun. 8, 2004 |
| 6748516 |
Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously |
Jun. 8, 2004 |
| 6718458 |
Method and apparatus for performing addressing operations in a superscalar, superpipelined processor |
Apr. 6, 2004 |
| 6487653 |
Method and apparatus for denormal load handling |
Nov. 26, 2002 |
| 6430681 |
Digital signal processor |
Aug. 6, 2002 |
| 6317825 |
Microprocessor comprising bit concatenation means |
Nov. 13, 2001 |
| 6088715 |
Close path selection unit for performing effective subtraction within a floating point arithmetic unit |
Jul. 11, 2000 |
| 6018756 |
Reduced-latency floating-point pipeline using normalization shifts of both operands |
Jan. 25, 2000 |
| 5963461 |
Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization |
Oct. 5, 1999 |
| 5905881 |
Delayed state writes for an instruction processor |
May. 18, 1999 |
| 5862067 |
Method and apparatus for providing high numerical accuracy with packed multiply-add or multiply-subtract operations |
Jan. 19, 1999 |
| 5835392 |
Method for performing complex fast fourier transforms (FFT's) |
Nov. 10, 1998 |
| 5646875 |
Denormalization system and method of operation |
Jul. 8, 1997 |
| 5590365 |
Pipeline information processing circuit for floating point operations |
Dec. 31, 1996 |
| 5559977 |
Method and apparatus for executing floating point (FP) instruction pairs in a pipelined processor by stalling the following FP instructions in an execution stage |
Sep. 24, 1996 |
| 5530663 |
Floating point unit for calculating a compound instruction A+B.times.C in two cycles |
Jun. 25, 1996 |
| 5517438 |
Fast multiply-add instruction sequence in a pipeline floating-point processor |
May. 14, 1996 |
| 5490100 |
Cumulative summation unit |
Feb. 6, 1996 |
| 5481748 |
Method and apparatus for reducing the processing time required to solve numerical problems |
Jan. 2, 1996 |
| 5307301 |
Floating point safe instruction recognition method |
Apr. 26, 1994 |
| 5268854 |
Microprocessor with a function for three-dimensional graphic processing |
Dec. 7, 1993 |
| 5267186 |
Normalizing pipelined floating point processing unit |
Nov. 30, 1993 |
| 5257216 |
Floating point safe instruction recognition apparatus |
Oct. 26, 1993 |
| 5212662 |
Floating point arithmetic two cycle data flow |
May. 18, 1993 |
| 5204829 |
Interleaving operations in a floating-point numeric processor |
Apr. 20, 1993 |
| 5155816 |
Pipelined apparatus and method for controlled loading of floating point data in a microprocessor |
Oct. 13, 1992 |
| 5128888 |
Arithmetic unit having multiple accumulators |
Jul. 7, 1992 |
| 5058048 |
Normalizing pipelined floating point processing unit |
Oct. 15, 1991 |
| 5053986 |
Circuit for preservation of sign information in operations for comparison of the absolute value of operands |
Oct. 1, 1991 |
| 5053987 |
Arithmetic unit in a vector signal processor using pipelined computational blocks |
Oct. 1, 1991 |
| 5053631 |
Pipelined floating point processing unit |
Oct. 1, 1991 |
| 4999802 |
Floating point arithmetic two cycle data flow |
Mar. 12, 1991 |
| 4996661 |
Single chip complex floating point numeric processor |
Feb. 26, 1991 |
| 4994996 |
Pipelined floating point adder for digital computer |
Feb. 19, 1991 |
| 4977534 |
Operation circuit based on floating-point representation with selective bypass for increasing processing speed |
Dec. 11, 1990 |
| 4931974 |
Sixteen-bit programmable pipelined arithmetic logic unit |
Jun. 5, 1990 |
| 4916652 |
Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures |
Apr. 10, 1990 |
| 4888682 |
Parallel vector processor using multiple dedicated processors and vector registers divided into smaller registers |
Dec. 19, 1989 |
| 4773035 |
Pipelined data processing system utilizing ideal floating point execution condition detection |
Sep. 20, 1988 |
| 4736335 |
Multiplier-accumulator circuit using latched sums and carries |
Apr. 5, 1988 |
| 4589067 |
Full floating point vector processor with dynamically configurable multifunction pipelined ALU |
May. 13, 1986 |
| 4208722 |
Floating point data processing system |
Jun. 17, 1980 |
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